Application of bi-layer resist on 70 nm node memory devices

Yool Kang; Jin Hong; Shi-Yong Lee; Hyung-Rae Lee; Man-Hyoung Ryoo; Sang-Gyun Woo; Han-Ku Cho; Joo-Tae Moon

doi:10.1117/12.599484

4 May 2005 Application of bi-layer resist on 70 nm node memory devices

Yool Kang, Jin Hong, Shi-Yong Lee, Hyung-Rae Lee, Man-Hyoung Ryoo, Sang-Gyun Woo, Han-Ku Cho, Joo-Tae Moon

Proceedings Volume 5753, Advances in Resist Technology and Processing XXII; (2005) https://doi.org/10.1117/12.599484
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

Bi-Layer Resist (BLR) process has been developed as an alternative method to overcome the limit of Single-Layer Resist lithography. Compared to other methods such as Single-Layer Resist (SLR) and Multi-Layer Resist (MLR), BLR has distinct advantages in cost down effect and quick Turn-Around-Time (TAT) due to the reduced number of process steps. In addition, it yields acceptional improvement in the Line-Width Roughness (LWR) on smaller CD. We have obtained feasible results of dense line and space patterning on various devices, which has 70 nm design rule. In this paper, a scanner of NA 0.85 is used and then appropriate condition of dry etch without any grass defect is developed. We are certain that BLR process is a strong candidate approach for the extension technology of ArF lithography and has potentially applicable in various devices.

Citation Download Citation

Yool Kang, Jin Hong, Shi-Yong Lee, Hyung-Rae Lee, Man-Hyoung Ryoo, Sang-Gyun Woo, Han-Ku Cho, and Joo-Tae Moon "Application of bi-layer resist on 70 nm node memory devices", Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (4 May 2005); https://doi.org/10.1117/12.599484

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