Paper
22 March 2011 Spacer defined double patterning for (sub-)20nm half pitch single damascene structures
Janko Versluijs, Yong Kong Siew, Eddy Kunnen, Diziana Vangoidsenhoven, Steven Demuynck, Vincent Wiaux, Harold Dekkers, Gerald Beyer
Author Affiliations +
Abstract
The spacer defined double patterning (SDDP) approach for 20nm half pitch (HP) single damascene Cu interconnect structures using immersion lithography is being reviewed. Final results on wafer will be shown, focusing on critical double patterning topics such as CD & overlay budget and line edge roughness (LER); and their impact on the electrical functioning of the back-end-of-line test structures. The feasibility of extending the SDDP technique down to 15nm HP structures is also discussed. The 30nm line/space structures patterned in resist, required as a starting point for this exercise, will be patterned using EUV lithography.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Janko Versluijs, Yong Kong Siew, Eddy Kunnen, Diziana Vangoidsenhoven, Steven Demuynck, Vincent Wiaux, Harold Dekkers, and Gerald Beyer "Spacer defined double patterning for (sub-)20nm half pitch single damascene structures", Proc. SPIE 7973, Optical Microlithography XXIV, 79731R (22 March 2011); https://doi.org/10.1117/12.881600
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Cited by 3 scholarly publications.
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KEYWORDS
Etching

Double patterning technology

Optical alignment

Optical lithography

Semiconducting wafers

Line edge roughness

Carbon

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