In this manuscript, this conventional issue will be demonstrated which is either over exposure in logic area or under exposure in bitcell area. The selective rule-based re-targeting concerning active layer will also be discussed, together with the improved wafer CDSEM data. The alternative method is to achieve different mean-to-nominal in different reticle areas which can be realized by lithography tolerance MPC during reticle process. The investigation of alternative methods will be presented, as well as the trade-off between them to improve the wafer uniformity and process margin of implant layers. |
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CITATIONS
Cited by 1 scholarly publication.
Reticles
Semiconducting wafers
Optical proximity correction
Logic
Lithography
Photomasks
Data modeling