Experimental investigation of three-dimensional interconnect processing wafers

Yi-sha Ku; Po-Yi Chang; Chris Shen

doi:10.1117/1.JMM.11.4.043002

1 October 2012 Experimental investigation of three-dimensional interconnect processing wafers

Yi-sha Ku, Po-Yi Chang, Chris Shen

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 11, Issue 4, 043002 (October 2012). https://doi.org/10.1117/1.JMM.11.4.043002

Abstract

The use and enhancement of a semi-automated wafer characterization tool, a dual channel capacitive sensor module, is demonstrated by implementing a new measurement algorithm for metallization process control. This tool is capable of measuring the deposited metal film thickness induced bow and warpage in a full wafer surface scan. The nondestructive solution can measure Cu metal film thickness with a total measurement uncertainty of 0.18 μm (1∂). The stress conversion map can be obtained based on the modified Stoney's formula and the capacitance-displacement technique. A wafer thinning process was also performed to characterize the warpage/bow of 8-in. wafers, which continues to increase as wafer thicknesses are reduced from 725 to 300 μm. There was a linear relationship between the wafer warpage and bow and the square of the inverse of the thickness. Metrology results from actual 3-D interconnect processing wafers are presented.

Citation Download Citation

Yi-sha Ku, Po-Yi Chang, and Chris Shen "Experimental investigation of three-dimensional interconnect processing wafers," Journal of Micro/Nanolithography, MEMS, and MOEMS 11(4), 043002 (1 October 2012). https://doi.org/10.1117/1.JMM.11.4.043002

Published: 1 October 2012

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