The interface which should correspond to Ohmic contact between the TiN bottom electrode and the TiN adhesive layer is investigated. However, from the measured V-I curve, a non-linear relationship is observed. The previous research and the replotted V-I curve using double-logarithmic scale demonstrate that an oxide layer at the interface is the major reason for the non-linear relationship and that the conduction mechanism here follows the Space-Charge-Limited- Current mechanism. To eliminate the interface effect, a pulse current with a compliance is introduced. A phenomenon is observed that negative resistance occurs because of the capture of filament in the oxide layer. As the width of pulse current increases, the interface effect is eliminated due to the formation of a permanent conducting filament. And , the VI curve shows a linear relationship, representing that the interface corresponds to Ohmic contact and the interface effect has been eliminated efficiently.
With Phase-change memory (PCM), information can be stored as different resistance states even when not powered. In order to accurately characterize the reliability of PCM devices, data retention has to be tested carefully. In this paper, a new test method is applied to measure the data retention of T-shaped PCM devices. This method makes it possible to accelerate crystallization in the amorphous area by using current bias. The new method works based on the field-induced crystallization theory, and could be able to gather fast and detailed information about high-resistance state’s failure process, and at the same time, it could avoid issues related to high temperature. Experimental data for T-shaped PCM devices based on Ge2Sb2Te5 are presented and analyzed. An exponential trend-line of failure time t versus reciprocal bias current 1/I shows only negligible deviation of the measured data points, enabling the extrapolation of the retention behavior for ten-year lifetime. A maximum disturb current value of 5.08 μA is extracted to guarantee the ten years data retention requirement for PCM applications.
Power on reset circuit provides a reset signal for the entire system into normal working condition. When power reaches normal operating voltage and remains stable, power on reset circuit provides one rectangular pulse signal which has a steep edge for the digital baseband part of the tag. After reset, POR circuit is isolated with the follow-up circuits, having good stability. In this paper, we designed two new static ultra-low power consumption power-on reset circuits. The first circuit uses Schmitt triggers for signal threshold detection and a certain delay. The peak current of the first circuit is 31uA, with a static current being 33 pA. The second circuit is based on a clamp circuit and PMOS gate cross-coupled circuit which greatly reduces the static current (190 pA). And the peak current of the second circuit is 21 μA.
Resistance distributions of the crystalline (SET) state and amorphous (RESET) state for phase change memory (PCM) are experimentally investigated at the array level. The RESET distribution shows a low resistance tail, which potentially affects the reading margin of the chip. These tail cells are divided into two types by resistance programming current (R-IP) and current voltage (I-V) characteristics. Finally, approaches of improving the integration process to remove the Type-1 tail cells and optimizing the programming operation to repair the Type-2 tail cells are proposed.
Circuit design of an adaptable pulse current source chip is presented in this paper. The pulse current source is supposed to be used to supply Reset and Set current in the phase change memory chip testing system. The value and width of the pulse current source are variable, with the maximum value of 10mA and minimum width of 50ns. Two pulse currents output simultaneously with the same width but different values. A voltage pulse input is used to control the width of pulse current output. This high frequency voltage pulse could induce noise jamming to the inner circuits. To avoid this, a novel ESD and bonding structure is proposed.
An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.
A write driver for PCM is designed to improve reliability and bit yield in the write operation, due to the distributions during the phase change process. And the PCM cell can be injected by current or voltage respectively. Meanwhile, owing to the possible variations of the SET process parameters, the designed circuit can generate either multiple stepdown current pulse or multiple step-down voltage pulse. The circuit is developed based on SMIC 130 nm CMOS standard technology. Compared to the traditional constant current pulse programming, the test results show that the proposed multiple step-down current generator for SET operation can improve the uniformity of resistance and bit yield.
A serial peripheral interface (SPI) 16-Kbit phase change memory chip based on 0.13μm CMOS process is designed. It contains a parallel error correcting code (ECC) circuit, which can correct 2 bits in every 8 bits without clock delay, enabling the write and read operations performed at bus speed. All the data transfers in 8-bit groups and can be read or written with write protection scheme by unlimited cycle, in which address can automatically increase one by one. Simulation results show that the chip can work correctly in SPI mode and with ECC scheme. It is now under testing.