KEYWORDS: Optical lithography, Etching, Metals, Photoresist materials, Capacitance, Transistors, Double patterning technology, Critical dimension metrology, Line edge roughness, Photoresist processing, Back end of line, Front end of line
The effects of photoresist sidewall profile and LER on two representative integration schemes were studied through 3D
virtual fabrication: Front-End of Line (FEOL) Fin formation and Back-End of Line (BEOL) Metal line definition. Both
of these processes use self-aligned double patterning (SADP) in pattern definition, and affect the circuit performance
through MOSFET channel shape and parasitic capacitance respectively. In both cases we imposed LER and sidewall
roughness on the photoresist that defines the mandrel at the initial step of the SADP flow using SEMulator3D. The LER
followed a Gaussian correlation function for a number of amplitude and correlation length values. The sidewall profile
emulated the bulb-shaped pattern that is reported in experimental works. The taper angle and roughness amplitude of this
shape were varied to isolate its components. In each of these cases, we have found direct evidence of resist sidewall
profile impact on variability degradation in CD and electrical performance. Special care should be placed on controlling
resist profile through optimization of exposure and development schemes.
For directed self-assembly (DSA) to be deployed in advanced semiconductor technologies, it must reliably integrate into a full process flow. We present a methodology for using virtual fabrication software, including predictive DSA process models, to develop and analyze the replacement of self-aligned quadruple patterning with Liu–Nealey chemoepitaxy on a 14-nm dynamic random access memory (DRAM) process. To quantify the impact of this module replacement, we investigated a key process yield metric for DRAM, interface area between the capacitor contacts and transistor source/drain. Additionally, we demonstrate virtual fabrication of the DRAM cell’s hexagonally packed capacitors patterned with an array of diblock copolymer cylinders in place of fourfold litho-etch (LE4) patterning.
Proc. SPIE. 9782, Advanced Etch Technology for Nanopatterning V
KEYWORDS: Lithography, Optical lithography, Spatial frequencies, Etching, Line width roughness, Deposition processes, Line edge roughness, Process modeling, Back end of line, Fin field effect transitor
For the first time, process impact on line-edge roughness (LER) and line-width roughness (LWR) in a back-end-of-line (BEOL) self-aligned quadruple patterning (SAQP) flow has been systematically investigated through predictive 3D virtual fabrication. This frequency dependent LER study shows that both deposition and etching effectively reduce high frequency LER, while deposition is much more effective in reducing low frequency LER. Spacer-assisted patterning technology reduces LWR significantly by creating correlated edges, and further LWR improvement can be achieved by optimizing individual process effects on LER. Our study provides a guideline for the understanding and optimization of LER and LWR in advanced technology nodes.
For Directed Self-Assembly (DSA) to be deployed in advanced semiconductor technologies, it must reliably integrate into a full process flow. We present a methodology for using virtual fabrication software, including predictive DSA process models, to develop and analyze the replacement of SAQP patterning with LiNe chemoepitaxy on a 14nm DRAM process. To quantify the impact of this module replacement, we investigate a key process yield metric for DRAM: interface area between the capacitor contacts and transistor source/drain. Additionally, we demonstrate virtual fabrication of the DRAM cell’s hexagonally-packed capacitors patterned with an array of diblock copolymer cylinders in place of LE4 patterning.
Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node.
To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond.
In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the world's smallest working SRAM cell.