With the latest immersion scanners performing at the sub-2 nm overlay level, the non-lithography contributors to the OnProduct-Overlay budget become more and more dominant. Examples of these contributors are etching, thin film deposition, Chemical-Mechanical Planarization and thermal anneal. These processes can introduce stress or stress changes in the thin films on top of the silicon wafers, resulting in significant wafer grid distortions. High-order wafer alignment (HOWA) is the current ASML solution for correcting wafers with a high order grid distortion introduced by non-lithographic processes, especially when these distortions vary from wafer-to-wafer. These models are currently successfully applied in high volume production at several semiconductor device manufacturers. An important precondition is that the wafer distortions remain global as the polynomial-based HOWA models become less effective for very local distortions. Wafer-shape based feed forward overlay corrections can be a possible solution to overcome this challenge. Thin film stress typically has an impact on the unclamped, free-form shape of the wafers. When an accurate relationship between the wafer shape and in-plane distortion (IPD) after clamping is established then feedforward overlay control can be enabled. In this work we assess the capability of wafer-shape based IPD predictions via a controlled experiment. The processinduced IPDs are accurately measured on the ASML TWINSCANTM system using its SMASH alignment system and the wafer shapes are measured on the Superfast 4G inspection system. In order to relate the wafer shape to the IPD we have developed a prediction model beyond the standard Stoney approximation. The match between the predicted and measured IPD is excellent (~1-nm), indicating the feasibility of using wafer shape for feed-forward overlay control.
Within the semiconductor lithographic process, alignment control is one of the most critical considerations. In order to realize high device performance, semiconductor technology is approaching the 10 nm design rule, which requires progressively smaller overlay budgets. Simultaneously, structures are expanding in the 3rd dimension, thereby increasing the potential for inter-layer distortion. For these reasons, device patterning is becoming increasingly difficult as the portion of the overlay budget attributed to process-induced variation increases. After lithography, overlay gives valuable feedback to the lithography tool; however overlay measurements typically have limited density, especially at the wafer edge, due to throughput considerations. Moreover, since overlay is measured after lithography, it can only react to, but not predict the process-induced overlay.
This study is a joint investigation in a high-volume manufacturing environment of the portion of overlay associated with displacement induced by a single process across many chambers. Displacement measurements are measured by Coherent Gradient Sensing (CGS) interferometry, which generates high-density displacement maps (>3 million points on a 300 mm wafer) such that the stresses induced die-by-die and process-by-process can be tracked in detail. The results indicate the relationship between displacement and overlay shows the ability to forecast overlay values before the lithographic process. Details of the correlation including overlay/displacement range, and lot-to-lot displacement variability are considered.
The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today’s manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield.
In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.
The understanding and control of stresses accumulated during device fabrication is becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for the management of overlay and depth of focus during lithography. This paper describes the use of a comprehensive stress inspection technology, the Coherent Gradient Sensing (CGS) interferometer, for the characterization of stress-induced overlay errors. Using CGS, stresses and wafer distortions induced by any upstream process (or series of processes) can be measured, and the relative contribution of stress-induced overlay associated with individual processes can be evaluated. The CGS technology has two key features that enable the application of stress metrology to lithographic overlay: 1) whole-wafer stress measurement with approximately 800,000 points on a 300mm wafer, 2) patterned wafer stress measurement that is highly insensitive to variations in device structures or materials, such that any location within a die or wafer can be characterized without the need for traditional test structures. Fundamentally, thin-plate theory relates the in-plane stresses in a thin film structure to in-plane strains and displacements. The in-plane displacements in the film due to stress are related to the lithographic overlay. The approach presented here demonstrates the relationship between stress gradients are related to in-plane displacements. Data from case-studies are presented that further shows the correlation between in-plane displacements, measured from wafer distortion and traditional measurement of overlay targets.