Three stencil masks with simple die layouts on 24 mm x 24 mm Si membranes are made to compare simulation and experiment on image placement (IP). A pseudo finite element (FE) modeling is adopted. Displacements predicted by simulation are found to be smaller than experimental values, but both agree qualitatively. Four stencil masks with die layouts that model on ULSI hole layers in 30% opening ratio and pattern arrangement are successfully made. Displacements are reduced to 1/4 by adopting IP correction. The IP correction of EB data is found to be a useful method of reducing IP error.
We have fabricated seven masks with different patterns on a 27 mm x 34 mm single-membrane for Low Energy Electron-beam Proximity Lithography (LEEPL) by the wafer-flow process. We have examined the membrane flatness and image placement (IP) accuracy, which are essential qualities to be assured. We summarize the results as follows: Masks with membranes of 13 MP and 20MPa stress satisfy the membrane flatness requirement of less than 2 μm while a mask with a 6 MPa membrane does not. Maps of the distortion induced by the wafer-flow process are obtained for the masks with 13 MPa and 20 MPa membranes and their performance is explained in terms of the contraction of the mask substrate. The out-of-plane distortion for a 3 mm x 3 mm block of dense hole patterns with an opening ratio, ranging from 10% to 40%, has been evaluated. The distortion induced by the block has been evaluated and the effect of the local magnification correction on the IP error is examined. Maps of the distortion induced by the wafer-flow process and 4 x 4 blocks of 10% and 20% opening are obtained for a mask with 13 MPa membrane and the distortion induced by the blocks is estimated in 3σ. The uncorrectable IP error for the mask with the blocks of 10% opening is estimated to be 10 nm (in 3σ), which satisfies the specification for LEEPL masks.
Masks for low energy electron proximity projection lithography (LEEPL) are fabricated starting with 200 mm silicon-on-insulator (SOI) wafers. The effect of the thickness of the buried oxide (BOX) layer of an SOI wafer on its flatness has been investigated. The wafer flatness is found to decrease as the BOX layer becomes thin. When the SOI layer (Si membrane) is not doped by B or P, the membrane has a compressive stress even for a 0.2 μm thick BOX layer. A monitor mask with image placement (IP) marks on a single-large (24 mm square) membrane area has been fabricated, starting with an SOI wafer with an 1.1 μm thick stress-controlled SOI layer and a 0.2 μm thick BOX layer. The internal stress of the membrane was 19 +/- 6 MPa (3σ) (tensile), and the membrane flatness was 0.8 μm. An ES chuck for an LSM-IPRO, which holds a mask in the method compatible with that in LEEPL exposure tools, has been installed. Chucking reduced the mask flatness from 22 μm to 10 μm while the membrane flatness was kept less than 1.0 µm. The dynamic repeatability of IP measurement was 7.6 nm (x) and 4.8 nm (y) in 3σ. The IP error of the monitor mask that had only IP marks was 17 nm (x) and 17 nm (y) in 3σ, satisfying the specification of 30 nm or less.