Overlay control continues to be a critical aspect of successful semiconductor lithography processing, with overlay control systems becoming more and more elaborate to meet the requirements of advanced semiconductor nodes. Sampling optimization is especially important including the number of overlay measurements to perform on each wafer, the number of wafers to measure per lot, and where exactly to measure on each wafer. Conventional sampling optimization methodology is to collect dense data for a short period and use this data to optimize the locations to measure on the wafer. In recent years, rule-based sampling was introduced to relax this data requirement and improve the time to result. However, in both scenarios, one single sample plan is generated in offline optimization, which is then used in high volume manufacturing (HVM) without change, hence named “static sampling”. In this paper, we introduce a “dynamic sampling” approach, where multiple rule-based sample plans are generated, that complement each other by measuring different locations on the wafer, while meeting spatial and population balancing criteria. These sample plans can then be used in an alternating manner on a per-wafer basis (wafer-by-wafer dynamic sampling) and per-lot basis (lot-by-lot dynamic sampling) in HVM. In this paper, we first demonstrate the risks and the inherent trade-offs associated with static sampling by using overlay budget breakdown and best/worst case advanced process control (APC) simulations. We then characterize the overlay control improvement potential of dynamic sampling schemes through APC simulations using multiple metrics: on-product overlay, rework overlay and monitoring accuracy. Finally, we calculate the on-product overlay versus throughput cost function analysis and determine which dynamic sampling scheme is the most useful for which throughput conditions.
In advanced technology nodes, the focus window becomes tighter to achieve smaller CD features while maintaining or improving product yields. During the past decades, focus spot monitoring (FSM) has been a critical topic in high-volume manufacturing, not only for minimizing the contamination impact on focus performance but also for scanner productivity concerns if wafer table cleaning needs to be executed. Although there is a dedicated FSM option combined with automatic wafer table cleaning from the exposure tools, the users often need to be careful to design the threshold and monitor the area by different products and layers, to prevent false positive alarmsthat impact the productivity of scanners. In some cases, a small focus spot threshold can cause more false positive alarms at the wafer edge area due to the edge roll-off effect on the wafer table and steep wafer topography, which brings difficulty to detecting small focus spots due to contamination. In our study, we compare the classic FSM provided by exposure tools to a newly developed automated FSM mechanism. There are several mathematical steps and approaches implemented into our new type of FSM to reduce false positive focus spot alarms. For comparison, we evaluated the performance of classic and new FSM methods on different layers, which showed special topography, edge roll-off effect, or strong intra-field signature. Finally, a new robust and user-friendly FSM method has been demonstrated and proven that even with a tight threshold, the false positive alarm especially around the wafer edge area can be fully eliminated.
KEYWORDS: Data modeling, Semiconducting wafers, Overlay metrology, Machine learning, 3D modeling, Lithography, Data acquisition, Wafer testing, Target detection, Process modeling
As a part of the semiconductor manufacturing process, an overlay measurement instrument is used to inspect overlay accuracy after exposure. The overlay measurement results are not only used to evaluate accuracy, but also to optimize exposure processing by calculating various offsets based on the measurement results and feeding them back to the exposure system. Increasing the number of overlay measurement points can help identify and compensate for local distortions including EPE (edge placement errors). However, it is not practical to perform overlay measurement for all wafers and all regions, therefore the better strategy for is performing correction through combining predicted results with actual measurement results. Canon is working with Macronix to develop the VMOM (Virtual Machine Overlay Metrology) system for predicting overlay measurement results. The VMOM method uses machine learning to study large amounts of data to derive the relationship between overlay error results and exposure system process variables that cause overlay error. A VMOM model was developed using 3D-NAND process data and overlay prediction accuracy and exposure process optimization were evaluated. This paper reports the development status of the VMOM system and the practical effects of the system.
Overlay is one of the critical parameters and directly impacts yield. Due to high metrology cost, only a small number of wafers are measured per lot. To this end, virtual metrology (VM) aims to provide valuable information about the nonmeasured wafers with little to no additional cost. VM leverages historical per-wafer measurements from exposure tools and processing equipment collected at previous process steps to report overlay on every wafer. As data-driven approaches gain more adoption in the semiconductor manufacturing, machine learning (ML) is a natural choice to tackle this task. In this paper, we present the strategies of learning overlay prediction models from exposure and process context data as well as the steps for achieving desired prediction performance, including data preparation, feature selection, best modeling methods, hyperparameters tuning and objective. We demonstrate our methodology on a large HVM dataset under stable APC conditions.
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