Complementary FET (CFET) is the most promising device architecture for post-nanosheet CMOS scaling. Monolithic CFET is considered as natural evolution of nanosheet. However, its process integration is much more complex than nanosheet because of high aspect ratio patterning and vertical edge placement control due to stacked N-P nanosheet channels. In this paper, we will discuss approaches to solve these challenges for ultimate CMOS device scaling.

As the limits of EUV single exposure direct printing are being explored there is a need for etch processes that can transfer small features and reduce defectivity. The implementation of high numerical aperture (NA) EUV scanner tool will allow for printing of sub-10 nm features in a single exposure. However, it reduces the depth of focus, thus requires thinner photoresist coatings. In preparation for high NA (0.55) we explore the etch implications of thin EUV photoresists. Here we show two different strategies for bridge defect reduction during etch and break elimination with selective deposition during the etch process.

The quest for high performance solutions is one of the key growth drivers for the electronics industry. While improvements in semiconductor device performance is achieved with traditional front-end scaling technology, it is widely expected that packaging technology will play a key role in meeting future form factor and performance requirements. The high cost of transitioning to new semiconductor technology nodes is changing the role of packaging and assembly in the electronics industry. New packaging solutions such as chiplets and heterogeneous integration are being adopted to achieve the economic advantages that were previously met with pure silicon scaling. Some of these options include silicon interposers, fan-out wafer level packages, embedded bridge solutions. These solutions promise to meet the performance requirements of the next decade, but there are equipment and process challenges that must be addressed to realize the full potential. Key equipment innovations and process solutions for meeting next generation production requirements in a cost-effective manner will be discussed in this presentation.

This conference presentation was prepared for the Advanced Etch Technology and Process Integration for Nanopatterning XII conference at SPIE Advanced Lithography + Patterning 2023.

The next-generation semiconductor fabrication process requires advanced plasma etch technology to find breakthroughs in bottleneck steps such as high-aspect-ratio etch. Due to the inherent complexities, the industrial fields are eager for predictable plasma process simulation, which can help the trial-and-error approach. Due to the above reasons, empirical technologies in semiconductor plasma processing have been responsible mainly for the fabrication of most semiconductor devices. As the semiconductor industries move on the 3D chip technologies, these approaches are confronted by severe limitations due to the absence of fast and cost-effective nanoscale simulation tools. Here, we present a realistic 3D feature profile simulation coupled with bulk plasma simulation, which can support the insight for the next-generation plasma process.

The structuring of optical substrates gained more significance than ever before and many current and future applications challenge common production processes in respect to either grating or substrate geometry. Reactive ion beam etching (RIBE) offers the flexibility to etch blazed, binary or slanted gratings with varying dimensional parameters in flat but also curved substrates. This contribution’s focus is to demonstrate how RIBE can be adapted to various applications by tailoring the etching process or the etching tool to meet specific grating requirements.

A fully error corrected quantum machine is one of the keys to unlocking the promise and potential of quantum computing. It is now widely accepted that this will require thousands if not millions of identical, highly coherent, interconnected qubits and highlights the increasing need for improving fabrication and scalability of current qubit implementations. Conventional qubit fabrication processes, many relying on lift-off, suffer from low yield and poor uniformity. We outline progress on realizing qubits in a 300 mm fabrication facility with state-of-the-art tooling and advanced process technology and demonstrate advantages of foundry compatible flows for both spin and superconducting qubits.

VCSEL technologies advances in Coherent Corp enabling new applications and performance. Integration of optics into VCSELs to allow beam shaping to enable better optics design and reduce package.

This conference presentation was prepared for the Advanced Etch Technology and Process Integration for Nanopatterning XII conference at SPIE Advanced Lithography + Patterning 2023.

Silicon photonics platforms leveraging 300mm manufacturing fabrication plants is a growing sector. This trend will continue as the demand for energy efficient data centers, advanced quantum computing architectures and AR/VR drive demand forward. GlobalFoundries is at the forefront of advanced photonics platforms implementation and have recently announced it is collaborating with industry leaders to deliver innovative, unique, feature-rich solutions to solve some of the biggest challenges facing data centers today. In this paper we investigate the impact of process manufacturing techniques typically used in advanced logic and memory on photonics waveguides uniformity improvement and smoothing. Some focus will be placed on the patterning process itself investigating effects of plasma VUV cure, direct current superposition and area selective deposition on resist for downstream line edge roughness and line width roughness impact. We will also review impact of silicon nitride film uniformity and top roughness smoothing on final waveguide optical performance. While silicon photonics features are much larger than logic features, process requirements to achieve required optical performance are stringent and will require innovative solutions to continue driving down optical losses.

Radicals have been effectively used for photoresist removal for many decades, however, most radical treatments have an energy distribution with high energy tails. This contributes to unwanted surface change or damage of other exposed materials. Tighter energy control is needed. We propose an ultra-low energy radical treatment with sufficient energy for surface modification but also a tighter energy distribution that minimizes unwanted film damage or loss. In this method, a reactive chemistry is introduced below the plasma generation region so that reactive radicals are generated indirectly though collision with inert metastable species.

This conference presentation was prepared for the Advanced Etch Technology and Process Integration for Nanopatterning XII conference at SPIE Advanced Lithography + Patterning 2023.

In this work, plasma ALE process was developed for ruthenium that involves plasma fluorination with C4F8 or CHF3 plasma and ion bombardment with Ar plasma in an inductively coupled plasma (ICP) reactor. Chemical sputtering threshold of C4F8 plasma is lower than that of CHF3 plasma owing to the higher F1s/C1s ratio fluorocarbon layers. The ALE window was confirmed with bias voltage of 150~210V. The etch per cycle (EPC) of ruthenium was determined to be 1.5 nm/cycle for C4F8 and 0.6 nm/cycle for CHF3. The EPC of ruthenium was self-limited with increasing Ar plasma etch time.

The continued acceleration in dimensional scaling of logic and memory semiconductor devices requires the integration of more emerging multifunctional materials, which demand more complex and aggressive chemical processes, thereby heightening the environmental, health and safety risks. To realize the sustainability in etch and patterning integration, a three pronged approach must be undertaken. First, new alternative gases must be developed to replace hydrofluorocarbon (HFC) gases. Next, mitigating strategies must be developed to minimize any downstream reaction that can cause serious health and safety incidents. Finally, non-HFC/non-halogen etch chemistries must be tested to demonstrate feasibility in patterning nano-scale structures.

This conference presentation was prepared for the Advanced Etch Technology and Process Integration for Nanopatterning XII conference at SPIE Advanced Lithography + Patterning 2023.

In this study we examine several innovations. In lithography, we introduce our latest progress on metal oxide resist (MOR) to extend defectivity window, improve photo-speed, and wafer uniformity control by leveraging new resist development techniques. On the plasma etch front, we focus on plasma-resist interactions and the impact of the pattern transfer process. Gas chemistry and plasma characteristics can modulate resist rectification, leading to a widening of the defectivity window and smoothing of pattern roughness. Especially, when reducing line-space pattern defectivity, correlations between plasma characteristics and microbridge defect numbers point to a proper process regime for patterning in the sub 30nm pitch era.

Ion shield plate equipped Microwave-ECR etcher was developed to enable reactive ion vertical etching and isotropic radical etching in one chamber. The radical etching of BCl3 could etch HfO2 (High-k) in the low-pressure region below 0.6 Pa. The addition of SiCl4 to BCl3 improved the selectivity to SiGe. For SiOC (Low-k), NF3/N2 gas chemistry can be used for highly selective etching to SiO2 and SiN. The radical etching of NF3/N2 has low carbon reduction than the reactive ion etching.