Dr. Kuang-Han Chen Profile

Dr. Kuang-Han Chen

at Siemens EDA

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Author

Publications (9)

Proceedings Article | 16 September 2022 Paper

Checkpointing in EDA application for tapeout operation

Kuang Han Chen, Soohong Kim, Hien Vu, Stephen Kim, Ming Feng Shen

Proceedings Volume 12325, 1232507 (2022) https://doi.org/10.1117/12.2641214

KEYWORDS: Optical proximity correction, Photomasks, Electronic design automation, Resolution enhancement technologies, SRAF, Data storage, Semiconducting wafers, Scattering

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Proceedings Article | 16 March 2016 Paper

Hotspot detection and removal flow using multi-level silicon-calibrated CMP models

Ushasree Katakamsetty, Jansen Chee, Yongfu Li, Colin Hui, Jaime Bravo, Tamba Gbondo-Tugbawa, Brian Lee, Kuang-Han Chen, Aaron Gower-Hall, Sang-Min Han

Proceedings Volume 9781, 97810K (2016) https://doi.org/10.1117/12.2219545

KEYWORDS: Chemical mechanical planarization, Manufacturing, Design for manufacturability, Semiconducting wafers, Silicon, Etching, Product engineering, Design for manufacturing, Data modeling, Calibration, Copper, Back end of line, Metals

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Proceedings Article | 16 March 2016 Paper

Characterization of shallow trench isolation CMP process and its application

Helen Li, ChunLei Zhang, JinBing Liu, ZhengFang Liu, Kuang Han Chen, Tamba Gbondo-Tugbawa, Hua Ding, Flora Li, Brian Lee, Aaron Gower-Hall, Yang-Chih Chiu

Proceedings Volume 9781, 978113 (2016) https://doi.org/10.1117/12.2219912

KEYWORDS: Chemical mechanical planarization, Front end of line, Back end of line, 3D modeling, Design for manufacturing, Process modeling, Manufacturing, Process engineering, Transistors, Copper, Calibration, Oxides, Data modeling, Polishing

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Chemical mechanical polishing (CMP) has been a critical enabling technology in shallow trench isolation (STI), which is used in current integrated circuit fabrication process to accomplish device isolation. Excessive dishing and erosion in STI CMP processes, however, create device yield concerns. This paper proposes characterization and modeling techniques to address a variety of concerns in STI CMP. In the past, majority of CMP publications have been addressed on interconnect layers in backend- of-line (BEOL) process. However, the number of CMP steps in front-end-of-line (FEOL) has been increasing in more advanced process techniques like 3D-FinFET and replacement metal gate, as a results incoming topography induced by FEOL CMP steps can no longer be ignored as the topography accumulates and stacks up across multiple CMP steps and eventually propagating to BEOL layers. In this paper, we first discuss how to characterize and model STI CMP process. Once STI CMP model is developed, it can be used for screening design and detect possible manufacturing weak spots. We also work with process engineering team to establish hotspot criteria in terms of oxide dishing and nitride loss.

As process technologies move from planar transistor to 3D transistor like FinFet and multi-gate, it is important to accurately predict topography in FEOL CMP processes. These incoming topographies when stacked up can have huge impact in BEOL copper processes, where copper pooling becomes catastrophic yield loss. A calibration methodology to characterize STI CMP step is developed as shown in Figure 1; moreover, this STI CMP model is validated from silicon data collected from product chips not used in calibration stage. Additionally, wafer experimental setup and metrology plan are instrumental to an accurate model with high predictive power.

After a model is generated, spec limits and threshold to establish hotspots criteria can be defined. Such definition requires working closely with foundry process engineering and integration team and reviewing past failure analysis (FA) to come up a reasonable metrics. Conventionally, a potential STI weak point can be found when nitride residues remains in the active region after nitride strip. Another source of STI hotspots occurs when nitride erosion is too much, and active region can suffer severe damage.

Proceedings Article | 16 March 2016 Paper

Model-based CMP aware RC extraction of interconnects in 16nm designs

Yongchan Ban, Sang Min Han, Eunjoo Choi, Tamba Gbondo-Tugbawa, Kuang Han Chen

Proceedings Volume 9781, 97810G (2016) https://doi.org/10.1117/12.2219118

KEYWORDS: Chemical mechanical planarization, Model-based design, Design for manufacturing, Etching, Design for manufacturability, Manufacturing, Metals, Copper, Capacitance, Resistance, Semiconducting wafers, Oxides

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Proceedings Article | 15 March 2012 Paper

In-design hierarchical DFM closure for DFM-clean IP

Vikas Tripathi, Jayathi Subramanian, Puneet Sharma, Kuang-Han Chen, Bala Kasthuri, Philippe Hurat, Larry Layton

Proceedings Volume 8327, 83270W (2012) https://doi.org/10.1117/12.916219

KEYWORDS: Chemical mechanical planarization, Design for manufacturing, Computer aided design, Lithography, Metals, Copper, Data modeling, Neodymium, Curium, System on a chip

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Proceedings Article | 5 April 2011 Paper

Accurately predicting copper interconnect topographies in foundry design for manufacturability flows

Daniel Lu, Zhong Fan, Ki Duk Tak, Li-Fu Chang, Elain Zou, Jenny Jiang, Josh Yang, Linda Zhuang, Kuang Han Chen, Philippe Hurat, Hua Ding

Proceedings Volume 7974, 79740S (2011) https://doi.org/10.1117/12.879310

KEYWORDS: Chemical mechanical planarization, Copper, Design for manufacturing, Calibration, Design for manufacturability, Manufacturing, Model-based design, Process modeling, Curium, Data modeling

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Proceedings Article | 5 April 2011 Paper

In-design DFM CMP flow for block level simulation using 32nm CMP model

Naya Ha, Jinwoo Lee, S. W. Paek, Kee Sup Kim, Kuang Han Chen, Aaron Gower-Hall, Tamba Gbondo-Tugbawa, Philippe Hurat

Proceedings Volume 7974, 79740W (2011) https://doi.org/10.1117/12.880899

KEYWORDS: Chemical mechanical planarization, Metals, Copper, System on a chip, Design for manufacturing, Manufacturing, Dielectrics, Polishing, Device simulation, Logic

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Proceedings Article | 11 March 2010 Open Access

Realizing a 45-nm system on chip in the age of variability

Laurent Le Cam, Andy Appleby, Philippe Hurat, Benoit Carpentier, Kuang-Han Chen, Nishath Verghese

Proceedings Volume 7641, 764106 (2010) https://doi.org/10.1117/12.848023

KEYWORDS: Lithography, Chemical mechanical planarization, Design for manufacturing, Model-based design, System on a chip, Manufacturing, Metals, Databases, Design for manufacturability, Semiconductors

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Proceedings Article | 13 March 2009 Paper

Hotspot detection and design recommendation using silicon calibrated CMP model

Colin Hui, Xian Bin Wang, Haigou Huang, Ushasree Katakamsetty, Laertis Economikos, Mohammed Fayaz, Stephen Greco, Xiang Hua, Subramanian Jayathi, Chi-Min Yuan, Song Li, Vikas Mehrotra, Kuang Han Chen, Tamba Gbondo-Tugbawa, Taber Smith

Proceedings Volume 7275, 72751R (2009) https://doi.org/10.1117/12.816556

KEYWORDS: Chemical mechanical planarization, Metals, Copper, Calibration, Data modeling, Manufacturing, Process modeling, Model-based design, Silicon, Physics

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