This paper presents a study on a new method to create exposure profiles that are optimized for selected die areas where patterning is critical. This new “region of interest leveling (L-ROI)” method caters for trends in the memory market, where intra-die topography with height steps between for instance cell and periphery areas is commonly observed for several 3D-NAND and DRAM device layers. The method takes advantage of the presence of (periphery) die areas where for some device layers patterning is less important than for other, more critical die areas, like the cell area in 3D-NAND. The L-ROI exposure profiles are insensitive to intra-die topography and to variation of the intra-die topography. They result in tighter focus uniformity (FU) in regions of interest, and thus in tighter CDU as well, than conventional exposures at the cost of an accepted performance degradation in other, non-care areas. Results of a study on a VNAND channel hole layer are presented, including focus performance simulation results and CDU measurement results from in-resist verification of L-ROI functionality on an immersion lithography scanner. The latter show a 31.7% CDU improvement with respect to conventional exposure mode.
Process window qualification using focus-exposure wafers is an essential step in lithography and a key use case for CD-SEM metrology. An automated analysis using the correlation between CD and focus/dose is easily possible but rarely done due to missing safety checks. Pattern fidelity that is analyzed by eye and problematic focus/dose conditions that may cause pattern degradation are excluded by hand. Specifically, when EUV lithography is utilized for exposing the most critical layers, roughness estimation becomes much more important, as it will restrict the process window further. We develop and describe unbiased and stable roughness estimates for contact hole patterns and integrate them into the process window analysis pipeline and inline monitoring routine. The analysis goes beyond simple roughness values and can detect a variety of possible CD-SEM measurement problems and shape deviations as well. Furthermore, we introduce a novel image-based machine-learning approach to detect outliers and quantify defective or abnormal patterns. Notably, the underlying model does not require knowledge of the types of CD features or design information for which outliers should be detected. We demonstrate that the approach can reliably detect local defects and a variety of other pattern anomalies. Using the generated visualizations, images with anomalous features can be flagged automatically and the locations of the defects or deviations are pinpointed. The approach yields not only the final missing piece in automated process window qualification, but also new opportunities to monitor pattern fidelity in lithographical semi-conductor processes.
The random error has been increased relative to the systematic error in overlay misalignment, as the Critical Dimension(CD) of semiconductor-design shrinks to under the 20 nm on DRAM and single-digit nanometer on Logic. The random error comprises diverse factors including non-lithography context, which caused by intricate process other than the scanner itself, hence it’s hard to control through conventional control methods using control knobs of scanner . In this study, we show that how effectively control and reduce on product overlay(OPO) error through making the most use of the conventional control knobs aided by machine learning. In addition to showing improved results, we address that conventional overlay feedback control with weighted moving average(WMA) can give rise to fluctuation of OPO error over entire wafer area, especially on the edge of wafer, due to the lack of control capability or flexibility. As a result, we show that 15.7% of OPO error can be trained and predicted for in-fab data and OPO has been improved from 2.29 nm to 2.08 nm or 9.2% on average over 5-steps of 1,201 lots with simulator.
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