In this work, we demonstrate a self-aligned litho-etch litho-etch (SALELE) process flow for 18nm pitch patterning of subtractive Ru structures. This process combines many individual steps from a standard damascene double patterning flow with a spacer pull process to adapt it for subtractive patterning. Requiring two EUV exposures, this process flow enables a broad design space comparable to existing SALELE solutions for damascene integrations. Utilizing this process flow, we have demonstrated successful patterning of complex designs including intertwined comb-serpentines and various mixed pitch patterns. We report matched resistance for both mandrel and non-mandrel resistors. Additionally, we demonstrate equivalent yields for 1mm long intertwined comb-serpentine structures with serpentines formed from both mandrel and non-mandrel patterns.
Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.
Voids in copper lines are a common failure mechanism in the back end of line (BEOL) of integrated circuits manufacturing, affecting chip yield and reliability. As subsequent process nodes continue to shrink metal line dimensions, monitoring and control of these voids gain more and more importance [1]. Currently, there is no quantitative in-line metrology technique that allows voids to be identified and measured. This work aims to develop a new method to do so, by combining scatterometry (also referred to as Optical Critical Dimension or Optical CD) and low-energy x-ray fluorescence (LE-XRF), as well as machine learning techniques. By combining the inputs from these tools in the form of hybrid metrology, as well as with the incorporation of machine learning methods, we create a new metric, referred to as Vxo, to characterize the quantity of void. Additionally, the results are compared with inline electrical test data, as higher amounts of voids were expected to increase the measured resistivity. This was not found to be the case, as the impact of the voids was much less of a factor than variation in the cross-sectional area of the lines.
Lithography faces an increasing number of challenges as errors in pattern overlay and placement become increasingly significant as scaling continues. The flexibility of removing a lithography step offers a significant advantage in fabrication as it has the potential to mitigate these errors. Furthermore, this strategy also relaxes design rules in semiconductor fabrication enabling concepts like self-alignment. The use of selective area atomic layer deposition with self-assembled monolayers that incorporate different side group functionalities was evaluated in the deposition of a sacrificial etch mask. Monolayers with weak supramolecular interactions between components (e.g. Van der Waals) were found to exhibit significant defectivity when depositing this material at and below 100nm feature sizes. The incorporation stronger supramolecular interacting groups in the monolayer design, such as hydrogen bonding units or pi-pi interactions, did not produce an added benefit over the weaker interacting components. However, incorporation of reactive moieties in the monolayer component enabled the subsequent reaction of a SAM surface generating a polymer at the surface and providing a more effective barrier, greatly reducing the number and types of defects observed in the selectively deposited ALD film. These reactive monolayers enabled the selective deposition of a film with critical dimensions as low as 15nm. The deposited film was then used as an effective barrier for standard isotropic etch chemistries, allowing the selective removal of a metal without degradation to the surrounding surface. This work enables selective area ALD as a technology by (1) the development of a material that dramatically reduces defectivity and (2) the demonstrated use of the selectively deposited film as an etch mask and its subsequent removal under mild conditions.
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