PROCEEDINGS ARTICLE | June 25, 1999
Proc. SPIE. 3676, Emerging Lithographic Technologies III
KEYWORDS: Oxides, Lithography, Electron beam lithography, Electron beams, Silicon, Aluminum, Beam shaping, Optical alignment, CMOS devices, Overlay metrology
In order to improve the overlay accuracy in electron lithography, we have investigated the optimization of alignment key that included a ratio of alignment key according to scanning beam size, an optimum key depth/width, and material's dependency. The alignment repeatability of key, has the same ratio with scanning beam size, appears good results as compared with the other ratio. Scanning beam size also correlates with an alignment key width. As a process sequence of CMOS device, the key width of under layer is changed by the thickness of deposited materials, because of the deposition on side-wall. Therefore, the scanning beam size should be optimized for each step. In each material, there exists the critical thickness not affecting on the alignment reading repeatability. The standard deviation, which is calculated by measurement of key position with critical thickness, is less than 20 nm. We have results of the critical thickness of various materials. SiO2 and Si3N4 do not affect on the alignment signal, but doped WSix, Al, and doped poly-silicon are very sensitive because of back-scattering electrons. Using the optimized align key of WSix/doped poly-Si, the standard deviation was less than 10 nm. Otherwise, non-conducting layer must be etched more than 7000 angstrom. In this case, the standard deviation is larger than that of conducting materials, as more than 20 nm. We have results of optimum condition of alignment key in order to enhance the overlay accuracy. The standard deviation of total overlay accuracy is less than 50 nm which corresponds to 150 nm design rules device fabrication.
