We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.
In this paper, we study the impact of topographic guide or template properties on pattern formation in a directed self-assembly (DSA) process. In particular, we investigate the relationship between free energy and defect generation or process robustness, and analyze the influence of guide affinity. The good correlation between experimental and simulation results confirms the role of certain setup parameters and process conditions on the DSA patterning.