Proc. SPIE. 10145, Metrology, Inspection, and Process Control for Microlithography XXXI
KEYWORDS: Oxides, Metrology, Logic, Statistical analysis, Etching, Germanium, Resistance, Scanning electron microscopy, 3D metrology, Process control, Critical dimension metrology, Algorithm development, Overlay metrology, Standards development, Back end of line, Fin field effect transitor
The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.
The miniaturization of semiconductors continues, importance of overlay measurement is increasing. We measured overlay with analysis SEM called Miracle Eye which can output ultrahigh acceleration voltage in 1998. Meanwhile, since 2006, we have been working on SEM based overlay measurement and developed overlay measurement function of the same layer using CD-SEM. Then, we evaluated overlay of the same layer pattern after etching. This time, in order to measure overlay after lithography, we evaluated the see-through overlay using high voltage SEM CV5000 released in October 2016. In collaboration between imec and Hitachi High-Technologies, we evaluated repeatability, TIS of SEM-OVL as well as correlation between SEM-OVL and Opt-OVL in the M1@ADI and V0@ADI process. Repeatability and TIS results are reasonable and SEM-OVL has good correlation with Opt-OVL. By overlay measurement using CV 5000, we got the following conclusions. (1)SEM_OVL results of both M1 and V0 at ADI show good correlation to OPT_OVL. (2)High voltage SEM can prove the measurement capability of a small pattern(Less than 1~2um) like device that can be placed in-die area. (3)"In-die SEM based overlay" shows possibility for high order control of scanner
With the continuous shrink in pattern size and increased density, overlay control has become one of the most critical issues in semiconductor manufacturing. Recently, SEM based overlay of AEI (After Etch Inspection) wafer has been used for reference and optimization of optical overlay (both Image Based Overlay (IBO) and Diffraction Based Overlay (DBO)). Overlay measurement at AEI stage contributes monitor and forecast the yield after formation by etch and calibrate optical measurement tools. however those overlay value seems difficult directly for feedback to a scanner. Therefore, there is a clear need to have SEM based overlay measurements of ADI (After Develop Inspection) wafers in order to serve as reference for optical overlay and make necessary corrections before wafers go to etch. Furthermore, to make the corrections as accurate as possible, actual device like feature dimensions need to be measured post ADI. This device size measurement is very unique feature of CDSEM , which can be measured with smaller area. This is currently possible only with the CD-SEM. This device size measurement is very unique feature of CD-SEM , which can be measured with smaller area. In this study, we assess SEM based overlay measurement of ADI and AEI wafer by using a sample from an N10 process flow. First, we demonstrate SEM based overlay performance at AEI by using dual damascene process for Via 0 (V0) and metal 1 (M1) layer. We also discuss the overlay measurements between litho-etch-litho stages of a triple patterned M1 layer and double pattern V0. Second, to illustrate the complexities in image acquisition and measurement we will measure overlay between M1B resist and buried M1A-Hard mask trench. Finally, we will show how high accelerating voltage can detect buried pattern information by BSE (Back Scattering Electron). In this paper we discuss the merits of this method versus standard optical metrology based corrections.
Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).
Overlay metrology accuracy is a major concern for our industry. Advanced logic process require more tighter overlay control for multipatterning schemes. TIS (Tool Induced Shift) and WIS (Wafer Induced Shift) are the main issues for IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). Methods of compensation have been introduced, some are even very efficient to reduce these measured offsets. Another related question is about the overlay target designs. These targets are never fully representative of the design rules, strong efforts have been achieved, but the device cannot be completely duplicated. Ideally, we would like to measure in the device itself to verify the real overlay value. Top down CDSEM can measure critical dimensions of any structure, it is not dependent of specific target design. It can also measure the overlay errors but only in specific cases like LELE (Litho Etch Litho Etch) after final patterning. In this paper, we will revisit the capability of the CDSEM at final patterning by measuring overlay in dedicated targets as well as inside a logic and an SRAM design. In the dedicated overlay targets, we study the measurement differences between design rules gratings and relaxed pitch gratings. These relaxed pitch which are usually used in IBO or DBO targets. Beyond this “simple” LELE case, we will explore the capability of the CDSEM to measure overlay even if not at final patterning, at litho level. We will assess the hybridization of DBO and CDSEM for reference to optical tools after final patterning.
We will show that these reference data can be used to validate the DBO overlay results (correctables and residual fingerprints).
One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.
One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (OVL) targets and actual device overlay error. In this study, we introduce the concept of Device Correlated Metrology (DCM), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking CD-SEM (Critical Dimension – Scanning Electron Microscope) target. The hybrid OVL target is designed to accurately represent the process influence found on the real device. In the general case, the CD-SEM can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of CD-SEM measurement uncertainty. Direct OVL measurements by CD-SEM show excellent correlation with optical OVL measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based OVL metrology methods using AIM or AIMid OVL targets, and scatterometry-based overlay methods such as SCOL (Scatterometry OVL). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.
Scanning electron-microscope (SEM) has been successfully applied to CD measurement as promising tools for qualifying and controlling quality of semiconductor devices in in-line manufacturing process since 1985. Furthermore SEM is proposed to be applied to in-die overlay monitor in the local area which is too small to be measured by optical overlay measurement tools any more, when the overlay control limit is going to be stringent and have un-ignorable dependence on device pattern layout, in-die location, and singular locations in wafer edge, etc. In this paper, we proposed new overlay measurement and inspection system to make an effective use of in-line SEM image, in consideration of trade-off between measurement uncertainty and measurement pattern density in each SEM conditions. In parallel, we make it clear that the best hybrid overlay metrology is in considering each tool’s technology portfolio.
As device design rule has been made pattern size shrink, overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic exposure tools, such as EUV and i-ArF scanners, require high-order overlay corrections. In conventional overlay metrology, several overlay targets are arranged in scribe area on product wafer. However, the number of measurement point is not sufficient for high-order overlay corrections and these positions are too far from device patterns to estimate its overlay. High-order overlay corrections should be calculated from overlay measurement data by using a considerable number of in-die targets near device pattern. In this case, smaller target area size is expected for advanced lithography. In this paper we introduce in-die overlay metrology by using critical dimension scanning electron microscope (CD-SEM). It has several advantages over a conventional optical overlay measurement tool, 1) the target area size can be set smaller than 5 x 5 μm, 2) the size and feature of measurement pattern can be set similar to device design, therefore WIS (Wafer Induced Shift) is assumed to be small, 3) TIS (Tool Induced Shift) by CD-SEM, which we measure, is small. Furthermore, we show repeatability and accuracy of the overlay measurement by CD-SEM. And overlay distribution measured by die-to-die can be verified by sufficient number of the dedicated targets in-die.