Deep neural networks (DNN) have been widely used in many applications in the past few years. Their capabilities to mimic high-dimensional complex systems make them also attractive for the area of semiconductor engineering, including lithographic mask design. Recent progress of mask writing technologies, including emergent techniques such as multi-beam raster scan mask writers, has made it possible to produce curvilinear masks with essentially “any” shapes. The increased granularity of mask shapes brings enormous advantages and challenges to resolution enhancement techniques (RET) such as optical proximity correction (OPC), Inverse lithography technologies (ILT), and other advanced mask optimization tools. Attempts of replacing the conventional segment based OPC by the ILT and other advanced solutions for full chip mask tapeout have been around for over a decade. Extremely slow mask data total-turnaround time is one of the major blocks. Therefore, its applications have been limited to small clip based applications such as for scanner source optimization, mask optimization only used for hotspot fixing and hierarchical memory designs. In this paper we present a new technique to apply DNN in our newly developed GPU-accelerated mask optimization platform, which reduces the runtime significantly without sacrificing the accuracy and convergence. This new tool combines deep learning, GPU computing platform and advanced optimization algorithms, and provides a fast and accurate solution for mask optimization in the sub-10nm tech nodes.
From 28 nm technology node and below optical proximity correction (OPC) needs to
take into account light scattering effects from prior layers when bottom anti-reflective coating
(BARC) is not used, which is typical for ionic implantation layers. These effects are complex,
especially when multiple sub layers have to be considered: for instance active and poly structures
need to be accounted for.
A new model form has been developed to address this wafer topography during model
calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification
(using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction
and verification. This paper discusses an exploration of this new model results using extended
wafer measurements (including SEM). Current results show good accuracy on various
KEYWORDS: Lithography, Electron beam lithography, Data modeling, Calibration, 3D modeling, Atomic force microscopy, Scanning electron microscopy, Double patterning technology, Data centers, Photoresist processing
The pursuit of ever smaller transistors has pushed technological innovations in the field of lithography. In order
to continue following the path of Moore’s law, several solutions have been proposed: EUV, e-beam and double
patterning lithography. As EUV and e-beam lithography are still not ready for mass production for 20 nm and 14 nm
nodes, double patterning lithography play an important role for these nodes. In this work, we focus on a Self-Aligned
Double-Patterning process (SADP) which consists of depositing a spacer material on each side of a mandrel exposed
during a first lithography step, dividing the pitch into two, after being transferred into the substrate, and then cutting the
unwanted patterns through a second lithography exposure.
In the specific case where spacers are deposited directly on the flanks of the resist, it is crucial to control its
profile as it could induce final CD errors or even spacer collapse. One possibility to prevent these defects from occurring
is to predict the profile of the resist at the OPc verification stage. For that, we need an empirical resist model that is able
to predict such behaviour.
This work is a study of a profile-aware resist model that is calibrated using both atomic force microscopy
(AFM) and scanning electron microscopy (SEM) data, both taken using a focus and exposure matrix (FEM).
Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage
of non-uniform reflective substrates without bottom anti-reflection coating (BARC).
Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer
topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects
such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without
BARC, e.g., implant layer, as technology node shrinks.
For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated
using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and
resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate
them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if
well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and
they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers
wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full
chip OPC on implant layers.
3D lithography simulations capable of modeling 3D effects in all lithographic processes are becoming critical in OPC
and verification applications as semiconductor feature sizes continue to shrink. These effects include mask topography,
resist profile and wafer topography. In this work we present an efficient computational framework for full-chip 3D
lithography simulations. Since fast modeling of mask topography effects has been studied for many years and is a
relatively mature area, we will only briefly review a full-chip 3D mask model, Tachyon M3D, to highlight the
importance and modeling requirements for accurate prediction of best focus variations among different device features
induced by mask topography. We will focus our discussions on a full-chip 3D resist model, Tachyon R3D, its derivation
and simplification from a full physical resist model. The resulting model form is fully compatible with the existing 2D
resist model with added capabilities for resist profile and top loss prediction. A benchmark against the full physical
model will be presented as well. We will also describe the development of a full-chip 3D wafer topography model,
Tachyon W3D, and the preliminary results against rigorous simulations.