28nm metal 90nm pitch is one of the most challenging processes for computational lithography due to the resolution limit of DUV scanners and the variety of designs allowed by design rules. Classical two dimensional hotspot simulations and OPC correction isn’t sufficient to obtain required process windows for mass production. This paper shows how three dimensional resist effects like top loss and line end shortening have been calibrated and used during the OPC process in order to achieve larger process window. Yield results on 28FDSOI product have been used to benchmark and validate gain between classical OPC and R3D OPC.
Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.
Advanced CMOS nodes require more and more information to get the wafer process well setup. Process tool intrinsic capabilities are not sufficient to secure specifications. APC systems (Advanced Process Control) are being developed in waferfab to manage process context information to automatically adjust and tune wafer processing. The APC manages today Run to Run component from and between various process steps plus a sub-recipes/profiles corrections management. This paper will outline the architecture of an integrated/holistic process control system for a high mix advanced logic waferfoundry.
The main difficulty related to DoseMapper correction is to generate an appropriate CD datacollection to feed
DoseMapper and to generate DoseRecipe in a user friendly way, especially with a complex process mix.
We could heavily measure the silicon and create, in feedback mode, the corresponding DoseRecipe. However, such
approach in a logic fab becomes a heavy duty due to the number of different masks / product / processes. We have
observed that process CD variability is significantly depending on systematic intrawafer and intrafield CD footprints that
can be measured and applied has generic pre-correction for any new product/mask process in-line. The applied CD
correction is based on a CD (intrafield: Mask + Straylight & intrawafer: Etch Bias) variability "model" handled by the
FAB APC (Advanced Process Control).
- Individual CD profile correction component are generated "off-line" (1) for Intrafield Mask via
automatic CD extraction from a Reticle CD database (2) for Intrafield Straylight via a CD "model" (3)
for Intrawafer Etch Bias via engineering input based on process monitoring.
- These CD files are handled via the FAB APC/automation system which is remotely taking control of
DoseMapper server via WEB services, so that CD profiles are generated "off-line" (before the lot is
being processed) and stored in a profile database while DoseRecipes are created "real-time" on
demand via the automation when the lot comes to the scanner to be processed. DoseRecipe and CD
correction profiles management is done via the APC system.
The automated DoseRecipe creation is now running since the beginning of 2011 contributing to bring both intrafield and
intrawafer GATE CDu below 1nm 3sigma, for 45/40 & 28nm nodes.