Mr. Simon Hsieh Profile

Simon Hsieh

Marketing at ASML CLS

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Author

Publications (6)

Proceedings Article | 18 March 2019 Presentation

Quantifying global and local CD variation for an advanced 3D NAND layer (Conference Presentation)

Will Conley, Yaobin Feng, Zhiyang Song, Moran Guo, Jun He, Longxia Guo, Gang Xu, Simon Hsieh, James Bonafede, Stephen Hsu, Austin Peng, Jun Wei Lu, Victor Peng, Beeri Nativ, Fei Jia, Herman Nicolai, Ijen van Mil

Proceedings Volume 10961, 109610J (2019) https://doi.org/10.1117/12.2515725

KEYWORDS: Critical dimension metrology, Light sources, Semiconducting wafers, Yield improvement, Deep ultraviolet, Scanners, Control systems, Source mask optimization

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Proceedings Article | 30 March 2017 Presentation + Paper

The impact of lower light source bandwidth on sub-10nm process node features

Will Conley, Paolo Alagna, Jason Shieh, Simon Hsieh, Tsann-Bim Chiou, Stephen Hsu, Greg Rechtsteiner

Proceedings Volume 10147, 1014707 (2017) https://doi.org/10.1117/12.2260210

KEYWORDS: Light sources, Process control, Image processing, Source mask optimization, Lithography, Critical dimension metrology, Optical proximity correction, Control systems, Overlay metrology, Optical lithography, Eye, Metrology, Electroluminescence

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Proceedings Article | 4 September 2015 Paper

Advanced process characterization of a 10nm Metal 1 Logic layer using light source modulation and monitoring

Paolo Alagna, Omar Zurita, Vadim Timoshkov, Patrick Wong, Greg Rechtsteiner, Jan Baselmans, Julien Mailfert, Will Conley, Simon Hsieh

Proceedings Volume 9661, 966105 (2015) https://doi.org/10.1117/12.2196862

KEYWORDS: Light sources, Semiconducting wafers, Optical lithography, Critical dimension metrology, Logic, Line width roughness, Optical proximity correction, Metals, Scanners, Modulation

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Proceedings Article | 18 March 2015 Paper

Impact of bandwidth on contrast sensitive structures for low k1 lithography

Will Conley, Simon Hsieh, Paolo Alagna, Yaching Hou, Pedro Martinez

Proceedings Volume 9426, 942607 (2015) https://doi.org/10.1117/12.2085826

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Scanners, Lithography, Control systems, Yield improvement, Optical proximity correction, Overlay metrology, Process control, Metals

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Proceedings Article | 12 December 2009 Paper

Model-based scanner tuning for process optimization

Tsung-Chih Chien, C. Y. Shih, R. C. Peng, H. H. Liu, Y. C. Chen, H. J. Lee, John Lin, K. W. Chang, C. M. Wu, W. H. Hung, Tommy Lee, H. C. Wu, X. Xie, W. J. Shao, C. H. Chang, R. Aldana, Y. Cao, R. Goossens, Simon Hsieh

Proceedings Volume 7520, 75201Q (2009) https://doi.org/10.1117/12.842551

KEYWORDS: Scanners, Semiconducting wafers, Calibration, Lithography, Yield improvement, Model-based design, Data modeling, Wafer-level optics, Optimization (mathematics), Process modeling

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Proceedings Article | 16 March 2009 Paper

Model-based scanner tuning in a manufacturing environment

C. Y. Shih, R. C. Peng, T. C. Chien, Y. W. Guo, J. Y. Lee, C. L. Chang, P. C. Huang, H. H. Liu, H. J. Lee, John Lin, K. W. Chang, C. P. Yeh, W. J. Shao, H. Cao, A. Bruguier, X. Xie, C. H. Chang, R. Aldana, Y. Cao, R. Goossens, Simon Hsieh

Proceedings Volume 7274, 72740T (2009) https://doi.org/10.1117/12.813974

KEYWORDS: Scanners, Semiconducting wafers, Data modeling, Calibration, Lithography, Manufacturing, Model-based design, Optical proximity correction, Wafer-level optics, Reticles

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Showing 5 of 6 publications

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