Defect reduction has become one of the most important technical challenges in device mass-production. Knowing that
resist processing on a clean track strongly impacts defect formation in many cases, we have been trying to improve the
track process to enhance customer yield. For example, residual type defect and pattern collapse are strongly related to
process parameters in developer, and we have reported new develop and rinse methods in the previous papers. Also, we
have reported the optimization method of filtration condition to reduce bridge type defects, which are mainly caused by
foreign substances such as gels in resist. Even though we have contributed resist caused defect reduction in past studies,
defect reduction requirements continue to be very important. In this paper, we will introduce further process
improvements in terms of resist defect reduction, including the latest experimental data.
Mass production of 193-nm immersion lithography has been started. Top coat process is one of the practical solutions for
applying the conventional dry ArF resists to achieve low material leaching and good scanning property, etc... At the
present, the lithographic world requires non-topcoat process from the point of view of C.O.O. (cost of ownership),
however there are still concerns that have to be revealed and solved. In order to achieve higher scan speed, the superior
water repellent property is required at the surface of non-topcoat resist. On the other hand, the influence of water
repellent surface property to the track process has to be considered. In this report, the considered items (coating,
development, etc...) of the higher water repellent property in non-topcoat process were extracted. Material design for
optimization of surface property with JSR non-topcoat resist and novel rinse method from process were proposed as
solutions to the concerns. Optimization of surface property showed positive impact to the development and defect
performance. The novel rinse method "ADR" which has been developed by Tokyo Electron showed superior availability
to reduction of blob type defect.
Residue type defect is one of yield detractors in lithography process. It is known that occurrence of the residue type
defect is dependent on resist development process and the defect is reduced by optimized rinsing condition. However, the
defect formation is affected by resist materials and substrate conditions. Therefore, it is necessary to optimize the
development process condition by each mask level. Those optimization steps require a large amount of time and effort.
The formation mechanism is investigated from viewpoint of both material and process. The defect formation is affected
by resist material types, substrate condition and development process condition (D.I.W. rinse step). Optimized resist
formulation and new rinse technology significantly reduce the residue type defect.
Nano-imprint lithography (NIL) is expected as one of the candidates for hp32nm to hp22nm technology nodes. NIL
needs 1X patterns on masks and a transit from 4X to 1X means a big and hard technology jump for the mask industry.
We have reported in previous papers that the resolution limit with 50keV acceleration voltage VSB (variable shaped
beam) electron beam writer, which are used in current 4X photomask manufacturing, was around 65nm. And we have
also reported that to reach the required resolution for hp32nm node, the usage of a 100keV acceleration voltage spot
beam writer would be inevitable.
Recently, we have installed a 100keV spot beam EB writer adjacent to our photomask manufacturing line. In this paper,
we will present our initial results with the tool. We have confirmed, after tuning of our process, a stable resolution
capability compatible for hp32nm. With this process, we have begun sample template manufacturing, and initial imprint
results are also presented. Templates with hp28nm dense line patterns were fabricated and were well imprinted.
As pattern feature sizes on the wafer become smaller and smaller, requirements for CD variation control has become a critical issue. In order to correct CD uniformity on the wafer, the DUV light transmission distribution of the photomask was altered using an ultra-fast pulsed laser technology. By creating a small scattering pixel inside the quartz body of the mask, a multitude of such points creates Shading Elements inside the quartz according to a predetermined CD variations distribution map. These Shading Elements reduce the dose of scanner's laser illumination onto the wafer per a local area. Thus by changing the local light intensity, inside the exposure field, to a required level during the photolithographic process the wafer CD is changed locally inside the field. This complete process of writing a multitude of Shading Elements inside the mask in order to control the light transmission and hence wafer level CD locally is called the CD Control (CDC) process.
We have evaluated the tool utilizing Ultra fast laser pulses (CDC 101) for local transmission and CD controllability on the wafer. We used Binary and Att-PSM test masks and three kinds of test patterns to confirm the sensitivity of transmission and CD change by the attenuation levels of Shading Elements which is sequentially changed from 0% to 10%. We will compare the AIMS results to printed CD on wafer or simulation results, so that we can correlate the transmission change and CD change by the attenuation levels. This paper also reports the CD uniformity correction performances by using attenuation mapping method on Binary mask. We also cover how Shading Elements affect the phase and transmission on the Att-PSM.
Nano-imprint lithography (NIL) is expected as one of the candidates for 32nm node and below. We reported in PMJ2005 that we could achieve 30nm resolution for isolated spaces and 50nm resolution for dense features with tools used in commercial mask shops today, and with modification of widely used resist. We also reported that the CD had shifted non-negligibly from the resist to quartz trench, due to the not-vertical pattern profile of the resist. In this paper, we review the resolution limit with current photomask manufacturing tools and the 100keV spot beam writer, and investigate the pattern line edge roughness. We also report our improvement in quartz dry-etch, in particular the improvement in the pattern profile and the etch depth linearity. We found by using the spot beam writer, we can potentially achieve 10nm isolated space and 35nm dense features, but we need to optimize the resist process.
Chrome-less Phase Lithography (CPL) technology is introduced as one of the key Resolution Enhancement Technologies for the application of 90 and 65nm node logic gate layer. From the view point of mask manufacturing, one of the strong points is that it doesn’t require complicated data division process into two complementary patterns, such as for double exposure AAPSM technology, and is possible to prepare the data by extension of EAPSM design technology. Another is the point of having a good wafer printing performance which is not inferior to AAPSM by giving the optimum exposure condition for a pattern. Although the optimization of OPC tuning is required, if a perfect mask manufacturing process is developed, it will be considered very feasible RET technology. While a mask process is important, establishment of inspection and repair technology is also very important. We have designed and fabricated a CPL defect test mask which has 90nm and 65nm technology nodes Line patterns for ArF lithography. By using this defect test mask, we will report defect detectability which was evaluated by several inspection systems. And also we will show the defect printability results by Zeiss MSM193 simulation microscope to confirm how the defect will affect to printing results. We also show repair performance of RAVE Nano-machining technology with the confirmation of printability by AIMS tool. Finally, we will discuss about when and how many inspections will be required in the CPL mask process.
The mask pattern edge profile's impact on critical dimension (CD) metrology and printing performance was investigated. Three 193nm attenuating PSMs with intentionally changed pattern edge profiles were made. The three masks had patterns with different CD data width, so that we could chose isolated lines and holes from each mask that gave almost the same CD when measured by a mask CD-SEM. We chose patterns that were measured approximately 400nm and 800nm for isolated lines, and approximately 500nm for isolated holes, and simulated their wafer CD by an AIMS tool and found not only that the AIMS results were different from the mask CD-SEM, but also that the difference was not constant for the three masks. Though in this work, the pattern edge profiles were intentionally changed and were far beyond the actual deviation range in current photomask manufacturing, this meant that the mask CD-SEM might face a difficulty in accurate wafer CD prediction if we should take the pattern edge profile into account. In this work we employed an atomic force microscope (AFM) based mask CD metrology tool, and by comparing the output profile with cross sectional SEM observation, we confirmed that the tool can observe the pattern edge profile nondestructively. If, at a certain slice, this tool can output the same CD as the AIMS for the three masks, we thought that this tool might be a promising candidate in wafer CD prediction. We found that the optimal slice level for the CD-AFM depended on the pattern category. For 400nm isolated lines, a 40% slice was optimal, while an 80% slice was optimal for 800nm isolated lines. For 500nm isolated holes, the range of 30 to 40% show good match between mask metrology and AIMS. Though the cause of this difference among pattern categories should be investigated further, from the fact that a certain slice can match the mask CD and AIMS, we concluded that the CD-SEM was a promising tool for wafer CD prediction.
As it is becoming clear that the 65nm node lithography would have no other alternative than "193nm" reinforced with all the possible RETs, "tricky" masks such as Alternating PSMs, Chromeless masks, or Enhancer masks might become inevitable. Most of the "tricky" masks will need the quartz substrate to be etched to give the phase shift. This means that an etching process without an etch-stop or an interface between different materials should be applied. We evaluated Qz etching process and optimized etching condition. Phase shift measurement system (λ 248 nm) and atomic force microscope were used for our measuring Qz depth and profile. And we can measure narrow space to 0.2 um size. As a result of optimized condition, Qz depth uniformity is 3sigma 1.5%, cross section is vertical sidewall and rectangular corner, and linearity error is 4.5% with isolated space and 9.0% at hole. And, we checked this linearity error does not affect so much to wafer printing, using aerial software simulation.