Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total critical dimension (CD) control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine via simulation the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state-of-the-art mask manufacturing data, and other variable changes are speculated, highlighting the need for improved metrology and communication between mask and optical proxmity correction model experts. The simulations are done by ignoring the wafer photoresist model and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the one-dimensional/two-dimensional representation of the mask, and for three-dimensional, the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.
Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, which must balance accuracy demands with simulation runtime boundary conditions, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned to wafer CD data over a small range around the presumed set point, it can be dangerous to do so since CD errors can alias across multiple input variables. Therefore, many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine with a simulation sensitivity study, the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD Bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and awareness.
Multiresolution writing refers to a technique used to simplify the data in one or more of the write passes
performed by a vector-based e-beam writer while maintaining the detail in at least one of the remaining layers. This
technique has been demonstrated to reduce the total shot count by as much as 30% with minimal predicted impact to
the mask features formed, and no predicted impact to the wafer lithographic results. We investigate the impact of
this technique on the mask manufacturing process. Specific mask parameters investigated include critical dimension
uniformity, critical dimension proximity and linearity effects, line edge roughness, and mask inspectibility.
Additional considerations include the applicability of this technique to existing mask designs as well as next
generation RET solutions. This characterization identifies an operating regime where shot savings can be realized
while still maintaining acceptable mask quality.
The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and
subsequently longer mask writing times. In particular inverse lithography methods create complex mask shapes. We
introduce a variety of techniques to mitigate the impact - data simplification post-optical proximity correction (OPC), L-Shots,
multi-resolution writing (MRW) and optimization based fracture. Their potential for shot count reduction is
assessed. All of these techniques require changes to the mask making work flow at some level - the data preparation and
verification flow, the mask writing equipment, the mask inspection and the mask qualification in the wafer
manufacturing line. The paper will discuss these factors and conduct a benefit - effort assessment for the deployment.
Some of the techniques do not reproduce the originally targeted mask shape. The impact of the deviations will be studied
at wafer level with simulations of the exposure process and quantified as to their impact on the exposure process
window. Based on the results of the assessment a deployment strategy will be discussed.
The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and
subsequently longer mask writing times. We review the data preparation steps post tapeout, how they influence shot
count as the main driver for mask writing time and techniques to reduce that impact. The paper discusses the application
of resolution enhancements and layout simplification techniques; the fracture step and optimization methods; mask
writing and novel ideas for shot count reduction.
The paper will describe and compare the following techniques: optimized fracture, pre-fracture jog alignment,
generalization of shot definition (L-shot), multi-resolution writing, optimized-based fracture, and optimized OPC output.
The comparison of shot count reduction techniques will consider the impact of changes to the current state of the art
using the following criteria: computational effort, CD control on the mask, mask rule compliance for manufacturing and
inspection, and the software and hardware changes required to achieve the mask write time reduction. The paper will
introduce the concepts and present some data preparation results based on process correction and fracturing tools.
Optical Proximity Correction (OPC) becomes complicated, shrinking a design rule. As a result, measurement points have
increased, and improving the OPC model quality has become more difficult. To improve OPC simulation cost,
Contour-based OPC-modeling is superior to CD-based, because Contour-based shape based rich information. Hence,
Contour-based OPC-modeling is imperative in the next generation lithography, as reported in SPIE2010[5].
In this study, Mask SEM-contours were input into OPC model calibration in order to verify the impact of mask pattern
shape on the quality of the OPC model. Advanced SEM contouring technology was applied to both of Wafer CD-SEM
and Mask CD-SEM in examining the effectiveness of OPC model calibration. The evaluation results of the model quality
will be reported. The advantage of Contour based OPC modeling using Wafer SEM-Contour and Mask SEM-Contour in
the next generation computational lithography will be discussed.
The increasing complexity of RET solutions with each new process node has increased the shot count of advanced
photomasks. In particular, the introduction of inverse lithography masks represents a significant increase in mask
complexity. Although shot count reduction can be achieved through careful management of the upstream OPC
strategy and improvement of fracture algorithms, it is also important to consider more dramatic departures from
traditional fracture techniques. Optimization based fracture allows for overlapping shots to be placed in a manner that
allows the mask intent to be realized while achieving significant savings in shot count relative to traditional fracture
based methods. We investigate the application of Optimization based fracture to reduce the shot count of inverse
lithography masks, provide an assessment of the potential shot count savings, and assess its impact on lithography
process window performance.
As design rules shrink, Optical Proximity Correction (OPC) becomes complicated. As a result, measurement points have
increased, and improving the OPC model quality has become more difficult. From the viewpoint of decreasing OPC
calibration runtime and improving OPC model quality concurrently, Contour-based OPC-modeling is superior to
CD-based OPC-modeling, because Contour-based OPC-modeling uses shape based rich information. Hence,
Contour-based OPC-modeling is imperative in the next generation lithography, as reported in SPIE2010.
In this study, Mask SEM-contours were input into OPC model calibration in order to verify the impact of mask pattern
shape on the quality of the OPC model. Advanced SEM contouring technology was applied to both of Wafer CD-SEM
and Mask CD-SEM in examining the effectiveness of OPC model calibration. The evaluation results of the model quality
will be reported. The advantage of Contour based OPC modeling using Wafer SEM-Contour and Mask SEM-Contour in
the next generation computational lithography will be discussed.
Temporal drift in the mask manufacturing process has been observed in CD measurements collected at different times.
Most of this is corrected through global sizing and dose adjustments resulting in small mean-to-target (MTT) residual
errors. However, this procedure does not account for a detectable change in the proximity behavior of the mask
process. This paper discusses a procedure for detecting and monitoring the proximity behavior of a process using an
targeted sampling plan. It also proposes a procedure to correct for drifts in proximity behavior if it is predictable and
systematic.
The extension of optical lithography at 193nm wavelength to the 32nm node and beyond drives advanced resolution
enhancement techniques that impose even tighter tolerance requirements on wafer lithography and etch as well as on
mask manufacturing. The presence of residual errors in photomasks and the limitations of capturing those in process
models for the wafer lithography have triggered development work for separately describing and correcting mask
manufacturing effects. Long range effects - uniformity and pattern loading driven - and short range effects - proximity
and linearity - contribute to the observed signatures. The dominating source of the short range errors is the etch process
and hence it was captured with a variable etch bias model in the past [1]. The paper will discuss limitations and possible
extensions to the approach for improved accuracy. The insertion of mask process correction into a post tapeout flow
imposes strict requirements for runtime and data integrity. The paper describes a comprehensive approach for mask
process correction including calibration and model building, model verification, mask data correction and mask data
verification. Experimental data on runtime performance is presented.
Flow scenarios as well as other applications of mask process correction for gaining operational efficiency in both tapeout
and mask manufacturing are discussed.
Design rule (DR) development strategies were fairly straightforward at earlier technology nodes when node-on-node
scaling could be accommodated easily by reduction of λ/NA. For more advanced nodes, resolution enhancement
technologies such as off-axis illumination and sub-resolution assist features have become essential for achieving full
shrink entitlement, and DR restrictions must be implemented to comprehend the inherent limitations of these techniques
(e.g., forbidden pitches) and the complex and unanticipated 2D interactions that arise from having a large number of
random geometric patterns within the optical ambit.
To date, several factors have limited the extent to which 2D simulations could be used in the DR development cycle,
including exceedingly poor cycle time for optimizing OPC and SRAF placement recipes per illumination condition,
prohibitively long simulation time for characterizing the lithographic process window on large 2D layouts, and difficulty
in detecting marginal lithographic sites using simulations based on discrete cut planes. We demonstrate the utility of the
inverse lithography technology technique [1] to address these limitations in the novel context of restrictive DR
development and design for manufacturability for the 32nm node. Using this technique, the theoretically optimum OPC
and SRAF treatment for each layout are quickly and automatically generated for each candidate illumination condition,
thereby eliminating the need for complex correction and placement recipes. "Ideal" masks are generated to explore
physical limits and subsequently "Manhattanized" in accordance with mask rules to explore realistic process limits.
Lithography process window calculations are distributed across multiple compute cores, enabling rapid full-chip-level
simulation. Finally, pixel-based image evaluation enables hot-spot detection at arbitrary levels of resolution, unlike the
'cut line' approach.
We have employed the ILT technique to explore forbidden-pitch contact hole printing in random logic. Simulations
from cells placed in random context are used to evaluate the effectiveness of restricting pitches in contact hole design
rules. We demonstrate how this simulation approach may not only accelerate the design rule development cycle, but
also may enable more flexibility in design by revealing overly restrictive rules, or reduce the amount of hot-spot fixing
required later in the design phase by revealing where restrictions are needed.
The use of sub-resolution assist features (SRAFs) is a necessary and effective
technique to mitigate the proximity effects resulting from low-k1 imaging with
aggressive illumination schemes. This paper investigates the application of one
implementation of Inverse Lithography Technology (ILT) to determine optimized SRAF
placement and size. In contrast to traditional rule-based methods in which SRAF
placement and size are typically predetermined and frozen in place, unmodified during
OPC, ILT allows for the simultaneous placement and sizing of SRAFs during target
inversion to maximize image quality while also maintaining margin against sidelobe
printing. Furthermore, ILT enables SRAF placement for random as well as periodic
patterns. In this paper, SRAF placement using this approach is studied through
simulations. The computed mask and simulation results are shown to illustrate
effectiveness of ILT-generated SRAF features.
An implementation of inverse lithography technology is studied with special attention to
illustrating and analyzing the placement, accuracy, and efficacy of subresolution assist elements.
One-dimensional placement through pitch is characterized, and 2D capability is demonstrated for
repeated patterns. Differences between the methods of mask preparation afforded by this system
as compared to current practices are described.
Inverse lithography technology (ILT) was studied during process development for four layers from memory semiconductor designs. This paper describes techniques used in each of the layers. So as to demonstrate this technology in a wide range of semiconductor patterns, we show results from all four layers. Polysilicon was chosen to demonstrate the selection of exposure/defocus (ED) points for constraining the inversion. Marking process window boundaries during a mask creation run was demonstrated on a contact hole layer. With a deep trench layer, mask constraints were varied and write times studied. Lastly, wafer SEM images were collected for an active layer to explore image fidelity though focus and CD stability along a line.
Inverse Lithography Technology (ILT), a mask creation technique with a decades-long history, has the potential for improving pattern fidelity and lithographic process window for features in dense memory ce lls (such as SRAM) for 100nm and 65nm nodes and beyond. Currently, the quality of OPC/RET/DfM/DfY methodology is verified based on CD
measurements. However, these measurements are not comprehensive enough, limited to a very few layout features. It is desirable to confirm lithographic process window robustly, for all the cell design features of interest, to ensure full functionality of the cell. In this work, we propose for the first time to focus on the electrical deliverables after ILT pattern quality has been initially verified by SEM visual inspection. We designed an electrically measurable SRAM
structure for a 65 nm process, to extract device and interconnect parameters depending on the lithographic process conditions, as a means to compare pattern quality of the conventional mask creation technique, Optical Proximity Correction (OPC) with ILT. We present the drawn layout, the masks created by the two technologies, and the
corresponding image simulation and silicon pattern.
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