Dr. Richard D. Peters Profile

Dr. Richard D. Peters

Engineering Research Staff

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Publications (15)

Proceedings Article | 29 March 2006 Paper

Gas-phase fluorination of resist for improving line-end pullback during etch

Richard Peters, Patrick Montgomery, Phillip Stout

Proceedings Volume 6153, 61532X (2006) https://doi.org/10.1117/12.654879

KEYWORDS: Etching, Photoresist materials, Photoresist processing, Optical proximity correction, Fluorine, Optical lithography, Chemistry, Lithography, Semiconducting wafers, 3D modeling

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Line-end pullback has been an issue for photoresist patterning for many years. The two-dimensional nature of line-ends leads to increased deprotection of the resist and shortening of the resist features. From a lithographic standpoint, line-end pullback can be mitigated to some extent using optical proximity correction (OPC). However, as the space between line-ends gets smaller, a trade-off exists with respect to OPC. Over-correction of the line-end on the reticle by the addition of hammerheads can lead to bridging. In some cases, the line-end spacing can actually be less than design rules. The poor aerial image contrast at these line-ends can lead to sloped profiles as well as pullback. The line-end slope depends on the resist contrast, the OPC, and the target line end-to-end space. These sloped line ends lead to increased pullback during the subsequent gate etch process. For gate patterning, a resist trim step is often utilized prior to etching a hardmask and polysilicon. During each etch step the resist line-end is quickly eroded due to the sloped profile. In this paper, we present a novel post-develop processing technique for improving the line-end profile of patterned photoresist. This improvement in the line-end profile results in less pullback during subsequent etch processing. After development, a patterned photoresist film is treated to a gas phase fluorination process. The fluorination process leads to substitution of F for H in the polymer matrix of the resist film, and causes the resist to swell. This swelling causes the line-end profile to become more vertical due to the fact that the base of resist features are anchored to the substrate, and only the top portion of the resist features will swell. This improvement in the line-end profile is shown to reduce line end-to-end spacing by 20-30% after etch. Cross-sectional images show the improvement throughout the partitioned etch process. Simulation results verify that a more vertical line-end slope is sufficient to decrease line-end pullback during etch.

Proceedings Article | 29 March 2006 Paper

Improved ion implantation masking through photoresist fluorination

Patrick Montgomery, Richard Peters, Cesar Garza, Terry Breeden, Marijean Azrak, Jack Jiang, Kiwoon Kim

Proceedings Volume 6153, 61532Y (2006) https://doi.org/10.1117/12.651047

KEYWORDS: Photoresist materials, Ions, Fluorine, Boron, Ion implantation, Semiconducting wafers, Silicon, Phosphorus, Chemical species, Semiconductors

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Proceedings Article | 12 May 2005 Paper

Applications of CPL mask technology for sub-65nm gate imaging

Lloyd Litt, Will Conley, Wei Wu, Richie Peters, Colita Parker, Jonathan Cobb, Bryan Kasprowicz, Doug van den Broeke, J. Park, Ramkumar Karur-Shanmugam

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600912

KEYWORDS: Reticles, Photomasks, Manufacturing, Inspection, Critical dimension metrology, Semiconducting wafers, Optical proximity correction, Lithography, Logic, Etching

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The requirements for critical dimension control on gate layer for high performance products are increasingly demanding. Phase shift techniques provide aerial image enhancement, which can translate into improved process window performance and greater critical dimension (CD) control if properly applied. Unfortunately, the application of hard shifter technology to production requires significant effort in layout and optical proximity correction (OPC) application. Chromeless Phase Lithography (CPL) has several advantages over complementary phase mask (c:PSM) such as use of a single mask, and lack of phase placement 'coloring' conflicts and phase imbalance issues. CPL does have implementation issues that must be resolved before it can be used in full-scale production. CPL mask designs can be approached by separating features into three zones based on several parameters, including size relative to the lithographic resolution of the stepper lens, wavelength, and illumination conditions defined. Features are placed into buckets for different treatment zones. Zone 1 features are constructed with 100% transmission phase shifted structures and Zone 3 features are chrome (binary) structures. Features that fall into Zone 2, which are too wide to be defined using the 100% transmission of pure CPL (i.e. have negative mask error factor, MEEF) are the most troublesome and can be approached in several ways. The authors have investigated the application of zebra structures of various sizes to product type layouts. Previous work to investigate CPL using test structures set the groundwork for the more difficult task of applying CPL rules to actual random logic design layouts, which include many zone transitions. Mask making limitations have been identified that play a role in the zebra sizing that can be applied to Zone 2 features. The elimination of Zone 2 regions was also investigated in an effort to simplify the application of CPL and improve manufacturability of reticle through data enhancements.

Proceedings Article | 4 May 2005 Paper

A novel contact hole shrink process for the 65-nm-node and beyond

Richard Peters, Patrick Montgomery, Cesar Garza, Stanley Filipiak, Tab Stephens, Dan Babbitt

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.599918

KEYWORDS: Photoresist processing, Cadmium sulfide, Fluorine, Optical lithography, Thermal effects, Scanning electron microscopy, Critical dimension metrology, Semiconducting wafers, Polymers, Semiconductors

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Proceedings Article | 20 August 2004 Paper

CPL reticle technology for advanced device applications

Willard Conley, Douglas Van Den Broeke, Robert Socha, Wei Wu, Lloyd Litt, Kevin Lucas, Bernard Roman, Richard Peters, Colita Parker, J. Fung Chen, Kurt Wampler, Thomas Laidig, Erika Schaefer, Jan-Pieter Kuijten, Arjan Verhappen, Stephan van de Goor, Martin Chaplin, Bryan Kasprowicz, Christopher Progler, Emilien Robert, Philippe Thony, Michael Hathorn

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557802

KEYWORDS: Photomasks, Optical proximity correction, Image processing, Reticles, Resolution enhancement technologies, Phase shifts, Mask making, Scanning electron microscopy, Quartz, Binary data

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Proceedings Article | 28 May 2004 Paper

The application of CPL reticle technology for the 0.045-mm node

Will Conley, Douglas Van Den Broeke, Robert Socha, Wei Wu, Lloyd Litt, Kevin Lucas, Bernard Roman, Richard Peters, Colita Parker, Fung Chen, Kurt Wampler, Thomas Laidig, Erika Schaefer, Jan-Pieter Kuijten, Arjan Verhappen, Stephan van de Goor, Martin Chaplin, Bryan Kasprowicz, Christopher Progler, Emilien Robert, Philippe Thony

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537613

KEYWORDS: Photomasks, Optical proximity correction, Reticles, Image processing, Resolution enhancement technologies, Phase shifts, Mask making, Scanning electron microscopy, Manufacturing, Quartz

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Proceedings Article | 20 May 2004 Paper

Process latitude measurements and their implications for CD control in EUV lithography

Jonathan Cobb, Richard Peters, Sergei Postnikov, Scott Hector, Bing Lu, Eric Weisbrod, James Wasson, Pawitter Mangat, Donna O'Connell

Proceedings Volume 5374, (2004) https://doi.org/10.1117/12.537366

KEYWORDS: Extreme ultraviolet lithography, Semiconducting wafers, Optical proximity correction, Lithography, Photomasks, Critical dimension metrology, Data modeling, Monte Carlo methods, Scanners, Scanning electron microscopy

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Proceedings Article | 14 May 2004 Paper

Single-layer and bilayer resist processes for EUV-type integrations

Richard Peters, Colita Parker, Jonathan Cobb, Eric Luckowski, Eric Weisbrod, Bill Dauksher

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.535643

KEYWORDS: Photoresist processing, Etching, Semiconducting wafers, Resistance, Scanning electron microscopy, Optical lithography, Extreme ultraviolet lithography, Image processing, Lithography, Line edge roughness

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Proceedings Article | 12 May 2004 Paper

Reduction of line edge roughness and post resist trim pattern collapse for sub 60 nm gate patterns using gas-phase resist fluorination

Patrick Montgomery, Richard Peters, Cesar Garza, Jonathan Cobb, Bill Darlington, Colita Parker, Stan Filipiak, Danny Babbitt

Proceedings Volume 5753, (2004) https://doi.org/10.1117/12.600785

KEYWORDS: Line edge roughness, Etching, Photoresist processing, Edge roughness, Fluorine, Silicon, Lithography, Yield improvement, Transistors, Scanning electron microscopy

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Proceedings Article | 12 June 2003 Paper

Controlling line-edge rougness to within reasonable limits

Jonathan Cobb, Shahid Rauf, Aaron Thean, S. Dakshina-Murthy, Tab Stephens, Colita Parker, Richard Peters, Vivek Rao

Proceedings Volume 5039, (2003) https://doi.org/10.1117/12.485169

KEYWORDS: Line edge roughness, Etching, 3D modeling, Diffusion, Process modeling, Instrument modeling, Photoresist processing, Photoresist materials, Edge roughness, Image processing

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Proceedings Article | 12 June 2003 Paper

Fabrication of integrated circuits with high yield using ultrathin resist processes

Richard Peters, Sergei Postnikov, Jonathan Cobb, S. Dakshina-Murthy, Tab Stephens, Colita Parker, Eric Luckowski, Arturo Martinez, Wei Wu, Scott Hector

Proceedings Volume 5039, (2003) https://doi.org/10.1117/12.485122

KEYWORDS: Photoresist processing, Transistors, Etching, Semiconducting wafers, Plasma etching, Plasma, Silicon, Resistance, Defect inspection, Optical lithography

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Proceedings Article | 12 June 2003 Paper

Ultrathin photoresists for 193-nm lithography

Richard Peters, Gilles Amblard, Jen-Jiang Lee, Todd Guenther

Proceedings Volume 5039, (2003) https://doi.org/10.1117/12.485132

KEYWORDS: Line edge roughness, Lithography, Photoresist processing, Photoresist materials, Scanning electron microscopy, Semiconducting wafers, Silicon, Fluorine, Ions, Mass spectrometry

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Fabrication of integrated circuits with sub-100 nm features will require tight control of critical dimensions, line edge roughness, and profiles of patterned features. The drive to smaller features will be accomplished principally by reduction of exposure wavelength in lithography systems. The use of 157 nm and EUV lithography will most likely require thin resists with thicknesses less than 150 nm due to the high absorption of materials at these wavelengths. High NA and low k1 systems for 193 nm lithography may also benefit from the use of thin photoresist processes. The properties and behavior of thin resists are expected to be strongly affected by interfaces, and thus, the lithographic performance of resists with sub-200-nm thickness is of interest. In this paper, we present a study of the lithographic behavior of a single layer 193 nm resist at different thicknesses ranging from 90 nm to 240 nm. The line edge roughness (LER) of 193 nm resist films increased dramatically with decreasing film thickness, but increasing the concentration of photoacid generator (PAG) and base quencher in the films helped reduce the LER. The process latitude for dense 110 nm lines (250 nm pitch) imaged using a single resist formulation with high PAG/quencher concentration was experimentally determined for 4 thicknesses (90 nm to 240 nm) by changing only the spin speed. The process latitude was found to be almost equivalent for sub-200 nm thick films, however, sub-100 nm thick films exhibited much higher LER than the thicker resist films. The performance of the 193 nm resist was compared to a 248 nm resist coated at thicknesses ranging from 104 nm to 260 nm. The 248 nm resist exhibited a decreasing trend in both exposure latitude and depth of focus with decreasing film thickness. Time-of-flight secondary ion mass spectrometry was used to investigate the distribution of PAG in the resist films. Some of the resist behavior of sub-150 nm thick films could be explained due to non-uniform PAG distribution.

Proceedings Article | 2 June 2003 Paper

Line-edge roughness reduction and CD slimming using hardbake processing

Richard Peters, Kevin Lucas, Jonathan Cobb, Colita Parker, Kyle Patterson, Robb McCauley, Monique Ercken, Frieda Van Roey, Nadia Vandenbroeck, Ivan Pollentier

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.485027

KEYWORDS: Line edge roughness, Monochromatic aberrations, Transistors, Scanning electron microscopy, 193nm lithography, Cadmium, Optical lithography, Extreme ultraviolet, Etching, Control systems

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Proceedings Article | 24 July 2002 Paper

Integration of UTR processes into MPU IC manufacturing flows

Jonathan Cobb, S. Dakshina-Murthy, Colita Parker, Eric Luckowski, Arturo Martinez, Richard Peters, Wei Wu, Scott Hector

Proceedings Volume 4690, (2002) https://doi.org/10.1117/12.474226

KEYWORDS: Etching, Line edge roughness, Photoresist processing, Semiconducting wafers, Scanning electron microscopy, Transistors, Optical lithography, Photoresist materials, Electron beam lithography, Image processing

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Proceedings Article | 24 July 2002 Paper

Development and characterization of 193-nm ultra-thin resist process

Gilles Amblard, Richard Peters, Jonathan Cobb, Kunishige Edamatsu

Proceedings Volume 4690, (2002) https://doi.org/10.1117/12.474227

KEYWORDS: Line edge roughness, Photoresist processing, 193nm lithography, Lithography, Semiconducting wafers, Fluorine, Scanning electron microscopy, Molecules, Scanners, Matrices

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Showing 5 of 15 publications

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