Journal of Micro/Nanolithography, MEMS, and MOEMS

Editor-in-Chief: Chris A. Mack, Lithoguru.com, USA

The Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3) publishes papers on the science, development, and practice of lithographic, fabrication, packaging, and integration technologies necessary to address the needs of the electronics, MEMS, MOEMS, and photonics industries. The wide range of such devices includes biomedical microdevices, microfluidics, sensors and actuators, adaptive optics, and digital micromirrors. The scope is broad to facilitate synergy and interest between the communities served by the journal.

Calls for Papers
How to Submit to a Special Section

To submit a manuscript for consideration in a Special Section, please prepare the manuscript according to the journal guidelines and use the Online Submission SystemLeaving site. A cover letter indicating that the submission is intended for this special section should be included with the paper. Papers will be peer‐reviewed in accordance with the journal's established policies and procedures. Authors who pay the voluntary page charges will receive the benefit of open access.

Control of Integrated Circuit Patterning Variance, Part 4: Placement and Critical Dimension, Edge to Edge Overlay
Publication Date
Special section papers are published as soon as the copyedited and typeset proofs are approved by the author.
Submission Deadline
Manuscripts due 1 November 2018.
Guest Editors
Alexander Starikov

I&I Consulting
Palo Alto, California, United States
alstarikov@gmail.com

Scope

Control of device dimensions in patterning is conventionally defined as consisting of two complementary components assumed to be independent: of size (linewidth or critical dimension, CD) and of placement (registration, wafer alignment, and layer to layer centerline to centerline overlay, OL). Two kinds of dimensional metrology are practiced for these two components, in dissimilar applications environments and typically on different tools, with process control and systematic corrections applied in two separate control loops. Control of edge-to-edge overlay (combination of two layers' CDs and OL), the design rule responsible for yield, is now widely recognized as limiting conventional lithography's progress.     

Lithography extensions through pitch multiplication and directed self-assembly lead to intermixing of CD and OL. Unlike in conventional lithography, where different physical mechanisms driving size variations and placement errors justify separate metrology and control, there is a strong need to self-consistently measure and control both CD and OL together. New approaches to IC patterning and the unprecedented expectations of device OL drive demand for complementary metrology and control of both pattern size and placement.

This special section of the Journal of Micro/Nanolithography, MEMS, and MOEMS seeks to offer comprehensive technology overviews of pattern placement, in-depth accounts of the latest technology and metrology equipment, pattern size and placement variation, metrology error, applications methods for control of size and placement, ultimately, of CD and edge-to-edge overlay in device layouts.  

Please submit a technology overview, a consolidation of earlier work, or an original technical paper related to metrology and control of pattern size and placement and device overlay in IC manufacture.  Topics of interest include, but are not limited to, the following:

Alignment, registration, and overlay metrology

  • Metrology of centerlines and the associated performance-limiting issues
  • Measurement self-consistency, matching, accuracy, cross-technology comparisons
  • Tool-related error mechanisms, their control and reduction, performance metrics
  • Metrology-design-process integration, metrology quality and performance metrics
  • Ultimate performance of metrology of pattern placement, hybrid metrology

Methods, technologies, and applications for control of edge-to-edge overlay

  • Device yield/performance and e-test versus in-line measurement of CD and OL
  • Sources of device size and placement variations, their signatures in space and time
  • Segmentation of device variance and control of its principal components
  • Modeling, prediction, and control of systematic variations, and of residual components
  • Design, metrology, and process integration for efficient high-volume manufacturing


All papers will undergo the standard peer-review process for the Journal of Micro/Nanolithography, MEMS and MOEMS (JM3). Manuscripts should be submitted to SPIE according to the journal's author guidelines. A cover letter indicating that the submission is intended for this special section should be included. For more information, please contact the Guest Editor or jm3@spie.org.


IC
Novel Patterning Technologies
Publication Date
Special section papers are published as soon as the copyedited and typeset proofs are approved by the author.
Submission Deadline
Closed for submissions.
Guest Editors
Eric Panning

Intel
Hillsboro, Oregon, United States
E-mail: eric.m.panning@intel.com

Martha Sanchez

IBM Research - Almaden
San Jose, California, United States
E-mail: marthasa@us.ibm.com

Scope

Extension of nanoscale patterning has been instrumental for the advancement of the semiconductor industry. Additionally, nanoscale patterning has potential to enable the commercialization of metamaterials, flat lenses, blaze gratings, and diffractive optical elements into new emerging applications. The range of applications for nanoscale patterning is now greater than ever; the traditional semiconductor industry now drives subnanometer precision, whereas many large-area nanopatterning applications require subdollar per square meter cost targets. Included in this list are patterned media for hard disk drives, photonic structure -enhanced high-brightness light-emitting diodes, optical waveguides for see-through augmented reality glasses, diffractive optical elements for 3D display, and more. It is now possible to unlock commercial value from almost all nanoscale patterning techniques when matched to the correct applications, including EUV lithography, directed self-assembly, nanoimprint, interference lithography, two-wavelength optical STED direct-write, multi-e-beam direct write, and more.

Any lithographic technology needs to address several key requirements beyond just resolution. Critical parameters include cost, defectivity, overlay, and throughput. In addition, any consideration for high-volume manufacturing must include a supporting infrastructure that facilitates a seamless integration of the new technology into a production facility. To address these key parameters and encourage the development of these technologies, we invite the submission of technical papers that will illustrate new applications for nanoscale patterning and aid in moving these lithographic technologies forward. Both theoretical and experimental papers are welcome in the following areas:

Directed Self-Assembly (DSA):

  • Design and integration strategies
  • Defect management, registration, and throughput
  • Metrology strategies and issues
  • Essential shapes, dimension control
  • Novel 2D and 3D DSA concepts and implementations
  • Novel materials, such as phase-segregating materials, molecular scaffolds, and molecular nanostructures
  • Predictive material, process, and compact models
  • Patterning of NIL templates and masks for non-IC applications such as hard disk drives

Alternative Pattern Integration Techniques:

  • Spacer multiple patterning
  • Self-aligned strategies
  • Selective deposition

Nanoimprint Lithography (NIL):

  • Thermal, UV, J-FIL, soft, and roll-to-roll imprint lithography, and novel imprint processes
  • Tooling and design, including alignment and overlay
  • Resists and novel materials
  • Defectivity, including defect sources and defect detection
  • Master and daughter mask/templates, including fabrication, metrology, cleaning, and replication
  • Nanometrology for NIL
  • Device fabrication using NIL

Direct-Write Maskless Lithography (ML2):

  • Single-beam or multibeam electron beam lithography (EBL) and ion-beam lithography
  • Massively parallel multibeam or multipixel EBL for wafer, mask, and template patterning
  • 2-wavelength STED optical direct write
  • Electro-optical MEMS technologies
  • Electron sources and optics, data path management, registration, and overlay control
  • Methods for achieving CD and LER control
  • High-throughput electron beam resists and resist processes

Other Novel Lithographic Approaches:

  • Including the use of plasmonics, micromirror optical lithography, interferometric lithography, tip-based nanolithography, scanning array lithography, dip pen printing, and drop-on-demand inkjet lithographyAlternative,

Non-IC Applications:

  • Including additive manufacturing, bioelectronics and genomics, photovoltaics and related energy applications, disk drives and patterned media, flat panel displays, optoelectronics and LEDs, photonic crystals, negative-refractive-index/meta materials, nanopatterned sensors, building blocks for defect tolerant computing, smart resists, and self-healing materials.

All submissions will be peer reviewed. Peer review will commence immediately upon manuscript submission, with a goal of making a first decision within 6 weeks of manuscript submission. Special sections are opened online once a minimum of four papers have been accepted. Each paper is published as soon as the copyedited and typeset proofs are approved by the author. Submissions should follow the guidelines of JM3. Manuscripts should be submitted online at https://jm3.msubmit.net.

For more information, please contact one of the guest editors or JM3@spie.org.

Novel Patterning
Control of Integrated Circuit Patterning Variance, Part 3: Pattern Roughness, Local Uniformity, and Stochastic Defects
Publication Date
Special section papers are published as soon as the copyedited and typeset proofs are approved by the author.
Submission Deadline
Closed for submissions.
Guest Editors
John C. Robinson

KLA-Tencor Corp.
Austin, Texas
E-mail: John.Robinson@KLA-Tencor.com

Tim Brunner

GLOBALFOUNDRIES, Inc.
Hopewell Junction, New York
E-mail: timothy.brunner@globalfoundries.com

Gian Lorusso

IMEC, Metrology Division
Leuven, Belgium
E-mail: Gian.Lorusso@imec.be 

Scope

Pattern variation due to stochastic processes is a significant problem for advanced semiconductor manufacturing. This variation can impact wafer patterning either quantitatively (CD uniformity, line-edge or linewidth roughness, edge placement error) or qualitatively (microbridges or breaks, closed or bridged contacts). Sources of stochastic variation include photo mask and lithography, as well as downstream processing such as etch, deposition, and cleans. While stochastic pattern variation is not a new problem, it becomes more challenging with smaller design rules where (1) feature roughness becomes an increasing percentage of the feature size, 10% to 20% in some cases, when (2) exposures of greater than 1 trillion features per wafer pass are expected to yield, and with (3) EUV lithography and its challenges of source power and throughput.

Integrated circuit (IC) patterning control addresses variance on multiple length scales. Longer length scales are typically characterized by critical dimension (CD) and placement (mask registration, wafer alignment, and layer-to-layer centerline overlay). Shorter length scale variability is characterized by line-edge roughness (LER), linewidth roughness (LWR), local CD uniformity (LCDU), pattern placement roughness, and defectivity. As the industry approaches sub-10 nm node design rules, the discrete nature of light due to shot noise (e.g., one contact may use as few as ~100 photons in an EUV exposure scenario) and the discrete nature of matter come into play. Even in cases where conventional continuum analysis would predict a sufficient process window, stochastic defects can occur due to the discrete nature of the light/matter interaction.   This special section of the Journal of Micro/Nanolithography, MEMS, and MOEMS seeks to offer technical contributions in the areas of LER, LWR, LCDU, and stochastic defectivity. Targeted disciplines include metrology, inspection, review, lithography, optical proximity correction (OPC) verification, etch processing, deposition, process integration, materials development, data science, algorithm development, electrical characterization, and yield analysis. Please submit a technology overview, a consolidation of earlier work, or an original technical paper related to:  

  • Metrology and inspection of roughness including CD scanning electron microscope (CD SEM), atomic force microscope (AFM), small angle x-ray scattering (SAXS), optical CD (OCD), focused ion beam (FIB), transmission electron microscope (TEM), optical defect inspection, e-beam defect inspection, and e-beam defect review
  • Methodologies to quantify roughness: edge detection, measurement algorithms, mathematical methods, power spectrum density (PSD), LER-bias characterization, statistical analysis
  • Roughness standards, reference metrology, and sampling
  • Roughness mitigation and control, OPC verification, stochastic process simulation
  • Material and process characterization: mask roughness, litho scanner systems, photoresist, resist processing, plasma smoothing, development of new resists, etch, deposition, and cleans
  • Roughness impact on device performance, electrical breakdown, circuit timing, and yield improvement
  • EUV stochastic defectivity levels, litho dose requirements by feature type and size, and mitigation methods
  • Design methodologies for stochastic fault tolerance.

All submissions will be peer reviewed. Peer review will commence immediately upon manuscript submission, with a goal of making a first decision within 6 weeks of manuscript submission. Special sections are opened online once a minimum of four papers have been accepted. Each paper is published as soon as the copyedited and typeset proofs are approved by the author. Submissions should follow the guidelines of JM3. Manuscripts should be submitted online at https://jm3.msubmit.net.

For more information, please contact one of the guest editors or JM3@spie.org.

IC Variance
Challenges and Approaches to EUV-Based Patterning for High-Volume Manufacturing Applications
Publication Date
Special section papers are published as soon as the copyedited and typeset proofs are approved by the author.
Submission Deadline
Manuscripts due 15 May 2018
Guest Editors
Sebastian Engelmann

IBM Research
1101 Kitchawan Road
Yorktown Heights, New York 10598
E-mail: suengelm@us.ibm.com

Rich Wise

Lam Research
4650 Cushing Parkway
Fremont, California 94538
E-mail: Rich.Wise@lamresearch.com  

Roel Gronheid

ICOS/KLA-Tencor Belgium
Esperantolaan 8
3001 Heverlee, Belgium
E-mail: roel.gronheid@kla-tencor.com  

Nelson Felix

IBM Research
257 Fuller Road
Albany, New York 12203
E-mail: nelfelix@us.ibm.com  

Scope

As EUV lithography (EUVL) approaches high-volume manufacturing (HVM) for semiconductor devices, many new challenges have emerged. To enable yield and the 7-nm and 5-nm nodes, and extend EUV to the 3-nm node and beyond, these multiple process, materials, and tooling challenges need to be addressed. We invite technical papers assessing these challenges and proposing solutions. Both theoretical and experimental papers are welcome in the following areas:

Advanced patterning processes
To enable single exposure at the 3-nm node (and potentially the 2-nm node), advanced patterning processes will be required. Feature control, quality, and productivity will have to be met. We invite papers on following topics:

  • etch challenges for 3D memory architectures
  • defect reduction or yield enhancement techniques by dry or wet process solutions
  • new etch methodologies and their application to patterning processes: atomic layer etching (ALE), low Te processing, etc.
  • advanced patterning, process, and selective deposition methods for novel etch-pattern transfer applications
  • novel patterning solutions for logic and memory applications.

Resist-litho-etch dependent processes
As we continue to evaluate EUV-based processes for advanced process nodes, increasing interdependence of lithography technologies, photoresist technologies, and plasma-etch technologies have created new opportunities in materials, integration, and the co-optimization of plasma-based patterning with lithography and process control. We invite papers on the following topics:

  • novel discoveries of plasma-material interactions: plasma-photoresist interactions, LER/LWR evolution, EUV resist interactions, MOL/BEOL (low-k) material interactions, novel substrate material handling (SiGe, III-V, C, nonvolatile memory), etc.
  • novel developments in plasma-based patterning techniques: EUV-based patterning, complementary patterning, self-aligned structures, on-product overlay, edge placement error mitigation strategies, and cost modeling of the proposed patterning schemes
  • patterning control through advanced process solutions: in-situ process control, process simulations, etch aware OPC, edge place error (EPE), etc.

EUV lithography enablement
To enable the implementation of EUV lithography for patterning in HVM and future nodes, challenges in multiple areas need to be addressed. These areas include imaging performance, exposure tooling improvements, EUV mask defectivity and inspection, novel stack materials, and defectivity and yield of patterning processes. We invite papers on the following topics:

  • new concepts in EUV imaging and resolution enhancement
  • EUV mask substrates and defectivity, including pellicle solutions
  • EUV mask inspection techniques
  • high-NA EUV enablement
  • double-patterning with EUV
  • patterning integration learning regarding total defectivity and yield.

All submissions will be peer reviewed. Peer review will commence immediately upon manuscript submission, with a goal of making a first decision within 6 weeks of manuscript submission. Special sections are opened online once a minimum of four papers have been accepted. Each paper is published as soon as the copyedited and typeset proofs are approved by the author. Submissions should follow the guidelines of JM3. Manuscripts should be submitted online at https://jm3.msubmit.net.

For more information, please contact one of the guest editors or JM3@spie.org.

Previously Published Special Sections

EUV Lithography for the 3-nm Node and Beyond (October-December 2017)
Guest Editors: Vivek Bakshi, Hakaru Mizoguchi, Ted Liang, Andrew Grenville, and Jos Benschop

Alternative Lithographic Technologies V (July-September 2016)
Guest Editors: Chris Bencher and Ricardo Ruiz

Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension (April-June 2016)
Guest Editor: Alexander Starikov

Photomask Manufacturing Technology (April-June 2016)
Guest Editors: Masato Shibuya, Morihisa Hoga, and Kiwamu Takehisa

Extending VLSI and Alternative Technology with Optical and Complementary Lithography (April-June 2016)
Guest Editors: Kafai Lai and Andreas Erdmann

On the Interface of Holography and MEMS (October-December 2015)
Guest Editors: Partha Banerjee, Pierre-Alexandre Blanche, Christophe Moser, and Myung K. Kim

Alternative Lithographic Technologies IV (July-September 2015)
Guest Editors: Douglas J. Resnick, Ricardo Ruiz, and Hans Loeschner

Control of Integrated Circuit Patterning Variance Part 1: Metrology, Process Monitoring, and Control of Critical Dimension (April-June 2015)
Guest Editors: Alexander Starikov and Matthew Sendelbach

Continuation of Scaling with Optical and Complementary Lithography (January-March 2015)
Guest Editors: Kafai Lai and Andreas Erdmann

Holistic/Hybrid Metrology (October-December 2014)
Guest Editors: Alok Vaid and Eric Solecky

Alternative Lithographic Technologies III (July-September 2014)
Guest Editors: Douglas J. Resnick, Christopher Bencher, and Ricardo Ruiz

Metrology and Inspection for 3-D Integrated Circuits and Interconnects (January-March 2014)
Guest Editors: Yi-sha Ku and Alexander Starikov

Emerging MOEMS Technology and Applications (January-March 2014)
Guest Editors: M. Edward Motamedi, Joel Kubby, Patrick Ian Oden, and Wibool Piyawattanametha

Optical Lithography Extension Beyond the 14-nm Node (January-March 2014)
Guest Editors: Will Conley and Kafai Lai

Advanced Fabrication of MEMS and Photonic Devices (October-December 2013)
Guest Editors: Georg von Freymann, Mary Ann Maher, and Thomas J. Suleski

Advanced Plasma-Etch Technology (October-December 2013)
Guest Editors: Ying Zhang, Qinghuang Lin, and Gottlieb S. Oehrlein

Alternative Lithographic Technologies (July-September 2013)
Guest Editors: Will Tong and Douglas J. Resnick

Photomasks for EUV Lithography (April-June 2013)
Guest Editors: Christopher J. Progler and Frank E. Abboud

Alternative Lithographic Technologies (July-September 2012)
Guest Editors: William M. Tong, Douglas J. Resnick, and Benjamin Rathsack

Directed Self-Assembly (July-September 2012)
Guest Editors: Daniel P. Sanders and William H. Arnold

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS III (April-June 2012)
Guest Editors: Sonia M. García-Blanco and Rajeshuni Ramesham

EUV Sources for Lithography (April-June 2012)
Guest Editors: Vivek Bakshi and Anthony Yen

Dimensional Metrology with Atomic Force Microscopy: Instruments and Applications (January-March 2012)
Guest Editors: Ronald Dixson and Ndubuisi G. Orji

Theory and Practice of MEMS, NEMS, and MOEMS (January-March 2011)
Guest Editor: Yu-Cheng Lin

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS II (October-December 2010)
Guest Editor: Rajeshuni Ramesham

Line-Edge Roughness (October-December 2010 )
Guest Editors: Chris A. Mack and Will Conley

Metrology (October-December 2010 )
Guest Editors: Moshe Preil and Shaunee Cheng

BioMEMS, Theory and Practice of MEMS/NEMS, and Sensors (July-September 2010)
Guest Editor: Yu-Cheng Lin

Extreme-Ultraviolet Lithography (October-December 2009)
Guest Editors: Kevin Cummings and Kazuaki Suzuki

Reliability, Packaging, Testing, and Characterization of MEMS and MOEMS (July-September 2009)
Guest Editors: Rajeshuni Ramesham and Allyson L. Hartzell

Computational Lithography (July-September 2009)
Guest Editors: Donis Flagello and Chris Mack

Theory and Practice of MEMS/NEMS/MOEMS, RF MEMS, and BioMEMS (April-June 2009)
Guest Editor: Yu-Cheng Lin

Extreme-Ultraviolet Interference Lithography (April-June 2009)
Guest Editor: Franco Cerrina

Double-Patterning Lithography (January-March 2009)
Guest Editor: William H. Arnold

Silicon-Based MOEMS and Their Applications (April-June 2008)
Guest Editors: Harald Schenk and Wibool Piyawattanametha

Resolution Enhancement Techniques and Design for Manufacturability (July-September 2007)
Guest Editor: Alfred K. K. Wong

Bio-MEMS and Microfluidics (April-June 2006)
Guest Editors: Wanjun Wang and Ian Papautsky

Nanopatterning (January-March 2006)
Guest Editors: Kees Eijkel, Jill Hruby, Glen Kubiak, M. Scott, Volker Saile, and Steven Walsh

MOEMS Design, Technology, and Applications (October-December 2005)
Guest Editor: M. Edward Motamedi

Polarization and Hyper-NA Lithography (July-September 2005)
Guest Editor: Donis Flagello and Christopher J. Progler

Next Generation Lithography (January-March 2005)
Guest Editor: Walt Trybula

Mask Technology for Optical Lithography (April-June 2004)
Guest Editor: Kevin D. Cummings and Frank M. Schellenberg

Immersion Lithography (January-March 2004)
Guest Editor: William H. Arnold

Surface Micromachining (October-December 2003)
Guest Editors: Jeffry J. Sniegowski and James H. Smith

Micro-Optics for Photonic Networks (October-December 2003)
Guest Editor: Thomas J. Suleski

Lithography for Sub-100-nm Device Fabrication (October-December 2002)
Guest Editor: William H. Arnold

Back to Top