Dr. Michael Crouse
Lithography Development Engineer at
SPIE Involvement:
Author
Publications (15)

PROCEEDINGS ARTICLE | March 18, 2016
Proc. SPIE. 9776, Extreme Ultraviolet (EUV) Lithography VII
KEYWORDS: Logic, Extreme ultraviolet lithography, Source mask optimization, Optical proximity correction, SRAF, Nanoimprint lithography, Line edge roughness, Semiconducting wafers, Stochastic processes, Resolution enhancement technologies

PROCEEDINGS ARTICLE | March 18, 2015
Proc. SPIE. 9427, Design-Process-Technology Co-optimization for Manufacturability IX
KEYWORDS: Lithography, Logic, Optical lithography, Etching, Scanners, Photomasks, Source mask optimization, Optical proximity correction, Semiconducting wafers, Process modeling

PROCEEDINGS ARTICLE | February 22, 2012
Proc. SPIE. 8326, Optical Microlithography XXV
KEYWORDS: Lithography, Monochromatic aberrations, Reticles, Calibration, Photomasks, Source mask optimization, Critical dimension metrology, Semiconducting wafers, Overlay metrology, Device simulation

PROCEEDINGS ARTICLE | May 18, 2011
Proc. SPIE. 8070, Metamaterials VI
KEYWORDS: Metamaterials, Metals, Annealing, Solar cells, Silicon, Resistance, Optical fabrication, Oxygen, Photoresist materials, Semiconducting wafers

PROCEEDINGS ARTICLE | March 23, 2011
Proc. SPIE. 7973, Optical Microlithography XXIV
KEYWORDS: Data modeling, Scanners, Silicon, Manufacturing, Scanning electron microscopy, Double patterning technology, Optical alignment, Critical dimension metrology, Semiconducting wafers, Overlay metrology

PROCEEDINGS ARTICLE | April 1, 2009
Proc. SPIE. 7273, Advances in Resist Materials and Processing Technology XXVI
KEYWORDS: Semiconductors, Lithography, Logic, Polymers, Scanning electron microscopy, Photomasks, Double patterning technology, Semiconducting wafers, Overlay metrology, Defect inspection

Showing 5 of 15 publications
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