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Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development.
Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.
In our work we utilize etch tools (Lam Kiyo® conductor etch systems) with proprietary edge tuning technology that can be used to reduce the etch-related asymmetry at the wafer edge. In combination to this unique method, we evaluate the impact of high order corrections per exposure field to compensate for process asymmetry at the wafer edge with a state-of-the-art 1.35 NA immersion scanner (NXT:1970Ci).
The study is done on dedicated test wafers with 10-nm logic node design. We use angle-resolved scatterometry (YieldStar® S-250), atomic force microscopy, and SEM cross-sections to characterize process asymmetry. We present experimental investigation of the effect of etch tuning and scanner corrections on the pattern shift and the resulting overlay. In particular, we present results showing a reduction of etch-induced pattern shift by 12nm at wafer radius 147mm.
Results show that asymmetry can be addressed by both, litho compensation and etch tuning, and bring on-product overlay down to the required level. We discuss the benefit of the correction techniques especially for thick hard mask layers (the pattern shift scales linear with hard mask thickness) and evaluate a combined correction scenario, where preventive etch tuning and feed-back based scanner corrections are used. We conclude that a holistic tuning of all process steps will be required to fulfill overlay requirements of future nodes.
Automatic pitch decomposition for improved process window when printing dense features at k1eff<0.20
This will count as one of your downloads.
You will have access to both the presentation and article (if available).
This course provides attendees with a basic working knowledge of the fundamentals and implementation principles of what industry calls with a generic name "double patterning” but in reality it is a multi-patterning technology. This course will tackle the interdisciplinary characteristics of the multipatterning processes examining several pitch division techniques, from double to triple, quadruple or even more split steps, with focus on the key technology components, such as, but not limited to, (a) resolution and lithography options, (b) layout, ground rules and split compliance, (c) process and material, that are combined to create an electrically functional device layer from multiple patterning steps. We will discuss single to multiple patterning pitch-split practical implementations adding complementary and combinatorial techniques based on pitch-divided gratings connected with a cut and/or a block masking layer.
The course presents the lithographic and patterning alternatives of various pitch-split techniques, for example, LithoEtch, LEn where n≥2 and multiple SelfAligned spacer film depositions, like SADP and SAQP. It will underline the interactions between layout style, split compliance, layer polarity, feature bias defined by split process characteristics and will draw attention to the constraints to integrate the pitch-split patterning steps into a complete CMOS process flow. In addition, the course provides information on the materials and material combinations used in multiple patterning processes illustrated by recent industry developments to increase the structural robustness of pitch divided high aspect ratio features and the anti-spacer / cut mask-less approach.
Special attention is given to the unique characteristics of multiple patterning metrology and process control, in particular to model overlay effects into comprehensive CDU budgets supporting the tight process tolerances of the scaling nodes. The course examines the CDU and overlay budget contributors and defines basic requirements for metrology tools performances to support multipatterning.
We will illustrate multipatterning utilization on today’s 3D transistors architecture, FinFet and Nanowires, applied on FEOL and BEOL layers, with unidirectional gratings and cuts or blocks that are needed to create the 2D layout intent. The course offers comprehensive analysis of the combinatorial multiple patterning flows, LE^n, SADP, SAQP with associated cut or block masking layers based on the new Edge Placement Error, EPE, metric, assessing pattern quality for manufacturability. Practical and useful examples from critical device layers of memory and logic devices are included throughout, with particular consideration on how multiple splits operate on device sequential layers using computational lithography optimized splits. The course includes extensive references of relevant publications on double/ multiple patterning processes.
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